549 Open source projects that are alternatives of or similar to ara

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Yet another toy CPU.

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

FPGA-based RISC-V CPU+SoC.

32-bit Superscalar RISC-V CPU

RISC-V processor emulator written in Rust+WASM

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

F# RISC-V Instruction Set formal specification

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V CPU Core (RV32IM)

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Unifying Python/C++/CUDA memory: Python buffered array ↔️ `std::vector` ↔️ CUDA managed memory

OpenGL vector map library - running on Android, iOS, Desktop and browser.

A macOS application displaying the thermal, voltage and current sensor values.

Project Planeverb is a CPU based real-time wave-based acoustics engine for games. It comes with an integration with the Unity Engine.

🐈 🐈 🐈 Running Cat

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

A simple script to log Linux CPU and memory usage (using top or pidstat command) over time and output an Excel- or OpenOfficeCalc-friendly report

Online batch converter of SVG images to Android vector drawable XML resource files

No description or website provided.

A tool to measure CPU core to core latency

MDEPX — A BSD-style RTOS

HW Design: A Functional Approach

Designed with Micriμm's renowned quality, scalability and reliability, the purpose of μC/ CPU is to provide a clean, organized ANSI C implementation of each processor's/compiler's hardware-dependent.

Milvus official website.

CPU and home computer project

A Folding@Home Docker container with GPU support

Highly portable Zilog Z80 CPU emulator written in ANSI C

Implementation of the MC6809 CPU in Python (Extracted from https://github.com/jedie/DragonPy project)

tiny fast portable real-time deep neural network for regression and classification within 50 LOC.

Automatic Differentiation using Pseudo Lenses. Neat.

Renderer using C++, Embree and USD to achieve Path Tracing techniques on the CPU

ARV: Asynchronous RISC-V Go High-level Functional Model

Riscv32 CPU Project

cpu command in Go, inspired by the Plan 9 cpu command

Project migrated to: https://gitlab.com/Oslandia/postile

Bash script to kill high CPU process, long running process and too much consuming memory process.

The Gee (寂) Operating System, written in YuLang.

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Code, documentation, schematics, notes for my Ben Eater inspired breadboard computer and emulator

Central Processing Unit Information Gathering Tool

Darknet on OpenCL Convolutional Neural Networks on OpenCL on Intel & NVidia & AMD & Mali GPUs for macOS & GNU/Linux

The squeezenet image classification android example

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Cross-platform lib for process and system monitoring in Python

⚡ Proof your app maintains 60-ish FPS by collecting data or showing it on screen with this NativeScript plugin!

✅ My own Amazon, Microsoft and Google SDE Coding challenge Solutions (offered by GeeksForGeeks).

NES emulator in Rust with GUI

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Go SDK for Milvus.

RISC-V RV32I[MAC] emulator with ELF support

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

RISCV SoftCPU Contest 2018

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

A pure Crystal Vector Math library