1097 Open source projects that are alternatives of or similar to Awesome Open Hardware Verification

A next-generation code testing stack for JavaScript.

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Classifies GPUs based on their 3D rendering benchmark score allowing the developer to provide sensible default settings for graphically intensive applications.

Code coverage metrics for Perl

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VHDL Samples

Dead simple testing framework for Bash with coverage reporting

This is the base project for the Mojo. It should be used as the starting point for all projects.

SD card based multi-purpose cartridge for the SNES

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SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

example for golang project using github actions

MIPS CPU implemented in Verilog

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

Testing Framework for PL/SQL

The Best Way to Get Started with your PulseSensor and Arduino

low cost software radio platform

TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

GameCube Digital AV converter

Sega Genesis for MiSTer

a gesture recognition verification lock

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

Fast and efficient ed25519 signing and verification in Rust.

CoreIR Symbolic Analyzer

⚔ Go package for data validation and filtering. support Map, Struct, Form data. Go通用的数据验证与过滤库，使用简单，内置大部分常用验证、过滤器，支持自定义验证器、自定义消息、字段翻译。

fast BAM/CRAM depth calculation for WGS, exome, or targeted sequencing

This is a higan/Verilator co-simulation example/framework

Bug-free machine learning on stochastic computation graphs

DDD patterns implemented following TDD

A Node.js library for interfacing with the Elgato Stream Deck.

Verilog and MIPS simple programs

Ansible provisioning framework - a set of modules, plugins, and documentation for provisioning with Ansible

State of the art mutation testing system for the JVM

Core sources and tools for the MIST board

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

Verilog AXI components for FPGA implementation

Otto DIY+ ("Otto DIY with steroids" + Bluetooth + APP + switch + sensors + strength +...

Cross-platform coverage gathering and processing tool set for .net/.net core and Mono

✅❎ A lightweight image rotation verification plugin.

Simple Theorem Prover, an efficient SMT solver for bitvectors

"SAT/SMT by example" free ebook

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Verifying concurrent crash-safe systems

A demonstration showing how several components can be compsed to build a simulated spectrogram

Gif RecyclerView in MVP using Dagger 2 + Retrofit 2 + Moshi + RxJava 2 + Glide 4 with JUnit and Espresso tests written in Kotlin + Kotlin DSL!

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This is the main repository for all the examples for the book Practical UVM

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HACL*, a formally verified cryptographic library written in F*

A Video display simulator

IC design and development should be faster，simpler and more reliable