741 Open source projects that are alternatives of or similar to Cores Swervolf

Badges for your GitHub tool presented at InfoSec Conference

A reimplementation of a tiny stack CPU

This utility allow downloading offline setup or deletion of old version Visual Studio 2017/2019 Offline Setup files and folder

The Antikernel operating system project

RetroBat is the best way to play your ROMs collection on Windows !

A single-wire bi-directional chip-to-chip interface for FPGAs

🛠 Lightweight utilities for string & array manipulation, image handling, safe JSON encoding/decoding, validation, slug or strong password generating etc.

A set of tools as React components for working with colors 🎨

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

android ui调试工具

Collection of small Java serviceability improvements based on JVM Tool Interface

A minimal DNS service that can provide spoofed replies

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

This repository is used to release the Labs of Computer Architecture Course from USTC

Elementary Java Components

Example designs showing different ways to use SymbiFlow toolchains.

Homotopy theory in Coq.

Tool to generate circles for block building games like Minecraft

A low pin count sniffer for ICEStick - targeting TPM chips

Скрипт для очистки каталога upload/iblock сайта на CMS 1С-Битрикс от неиспользуемых файлов (оставшихся после удаления элемента инфоблока).

⚔️ Web Hacker's Weapons / A collection of cool tools used by Web hackers. Happy hacking , Happy bug-hunting

🔎 Gitignore file generator written in rust

Exploit pack for pentesters and ethical hackers.

This is the main repository for all the examples for the book Practical UVM

tcp,websocket,webapi性能测试工具

Fixes simple parse errors automatically. Works great in combination with goimports.

FPGA 101 - Workshop materials

python3写的综合扫描工具，主要用来存活验证，敏感文件探测(目录扫描/js泄露接口/html注释泄露)，WAF/CDN识别，端口扫描，指纹/服务识别，操作系统识别，POC扫描，SQL注入，绕过CDN，查询旁站等功能，主要用来甲方自测或乙方授权测试，请勿用来搞破坏。

Tools to Design or Visualize Architecture of Neural Network

A nicer HDL.

Sega Genesis for MiSTer

UI tools to help make your Android app accessible.

Hacker tools on Go (Golang)

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

A very primitive but hopefully self-educational CPU in Verilog

Kali Linux 工具合集中文说明书

一个实用的windows小工具集合，里面包含了多个常用的小软件。其中的批量修改文件名及文件内容功能，可以自定义修改规则，支持规则的导入与导出。不需要安装Office软件，支持Excel/Word/Txt等文件的文件名或文件内容的批量修改操作。另外还包括正则表达式测试小工具、字符串转js常量工具、加密与解密和日期时间差等，您也可以很方便地扩展相关功能。

A Free and Comprehensive Encrypt and Decrypt Tools Website with example code in Node.js, Website is looking for a new server.

FPGA-based C64 Accelerator / C65 like computer

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

FPGA implementation of Cellular Neural Network (CNN)

High throughput JPEG decoder in Verilog for FPGA

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Mobile app for calculation of gasoline/oil ratio for 2 stroke engines built with React Native.

Common tools used by the GCP runtimes.

CDBUS Protocol and the IP Core for FPGA users

"Alfred for Xcode" plugin

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Regression test suite for Icarus Verilog.

A simple, dependency-free GDB stub that can be easily dropped in to your project.

FPGA-based RISC-V CPU+SoC.

go util 是golang通用工具包,实现一站式,开箱即用

IC design and development should be faster，simpler and more reliable

The best Hacking and PenTesting tools installer on the world

Alfred Workflow to calculate anything with natural language

The UI of HTTP Toolkit

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Bitcoin miner for Xilinx FPGAs