397 Open source projects that are alternatives of or similar to Cosa

Experimental Smart Contracts In Plutus.

Software Quality Wiki

TLA+ language support for Visual Studio Code

Read-only mirror of the Klever Git repository

TLA+ language support for Visual Studio Code

Reads a state transition system and performs property checking

Intrepyd Model Checker

Links to tools by subject

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

CAN Protocol Controller

Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)

The 99 Traveling Salespeople Project

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.

Haskell to VHDL/Verilog/SystemVerilog compiler

Change the pitch of your voice in real-time!

model-describer : Making machine learning interpretable to humans

Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module

mystorm sram test

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

FPGA-based glitcher for the Digilent Arty FPGA development board.

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

A (very) minimal web browser for FPGAs implemented in Verilog

Contains examples to start with Kactus2.

related to Spartan6 FPGA

SDRAM controller with multiple wishbone slave ports

High Speed Analog Front End FPGA Firmware for Novena PVT1

Image Processing Toolbox in Verilog using Basys3 FPGA

Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!

Barerbones OSX based Verilog simulation toolchain.

A demonstration showing how several components can be compsed to build a simulated spectrogram

Verilog and MIPS simple programs

tf530

CNN accelerator

A Lenet ASIC Accelerator targeting minimum number of cycles

❄️ Visual editor for open FPGA boards

A very simple VGA controller written in verilog

writing correct lock-free and distributed stateful systems in Rust, assisted by TLA+

1801 series ULA reverse engineering

This is a higan/Verilator co-simulation example/framework

KT-Link compatible buffer for the Bus Blaster v3

Galaksija computer for FPGA

A CPU that implementing THCO-MIPS16 instruction set.

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

G.729 Encoder

This repo is for the 4618 group nember to share code.

a programmable cryptographic coprocessor in verilog

Lean mathematical components library

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

collaboration on work in progress

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

HDL libraries and projects

Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.

Verilog Ethernet components for FPGA implementation

Meaningful control of data in distributed systems.

FPGA/AES/LeNet/VGG16

Verilog implementation of the SHA-512 hash function.