111 Open source projects that are alternatives of or similar to freedom-u-sdk

SiFive OpenEmbedded / Yocto BSP Layer

Example code included in the "Improving Your Embedded Linux Security Posture with Yocto" whitepaper

OpenEmbedded layer for the IOTA Distributed Ledger

Seamless container setup for developing with OpenEmbedded/Yocto Project

Setup tool for bitbake based projects

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

homebrew (macOS) packages for RISC-V toolchain

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Rocket Chip Generator

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

RISC-V processor emulator written in Rust+WASM

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

OpenEmbedded/Yocto layer for RISC-V Architecture

SweRV EH1 core

F# RISC-V Instruction Set formal specification

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

SweRV EL2 Core

A self-hosting and educational C compiler

Shakti: development platform for PlatformIO

ncnn is a high-performance neural network inference framework optimized for the mobile platform

FPGA 101 - Workshop materials

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Quasar 2.0: Chisel equivalent of SweRV-EL2

RISC-V simulator for x86-64

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

RARS -- RISC-V Assembler and Runtime Simulator

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

OpenEmbedded Layer for Home Assistant - An open-source home automation platform running on Python 3

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

riscv资料、论文等

RISC-V Assembler and Runtime Simulator

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

FPGA-based RISC-V CPU+SoC.

Maxine VM: A meta-circular research VM

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Tengine is a lite, high performance, modular inference engine for embedded device

Riscy Processors - Open-Sourced RISC-V Processors

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

An unofficial reference sheet for RISC-V.

Nuclei Microcontroller Software Interface Standard Development Repo

Tests for example Rocket Custom Coprocessors

xv6-riscv like OS written in Rust

Simple RISC-V 3-stage Pipeline in Chisel

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

A FPGA friendly 32 bit RISC-V CPU implementation

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

⛔ DEPRECATED ⛔ HERO Software Development Kit

SonicBOOM: The Berkeley Out-of-Order Machine