549 Open source projects that are alternatives of or similar to K1801

a general library for fatigue and reliability

Small footprint and configurable PCIe core

High performance motor control

Notes on the Red Pitaya Open Source Instrument

A full-speed device-side USB peripheral core written in Verilog.

FPGA-based Nintendo Entertainment System Emulator

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

PCIe (1.0a to 2.0) Virtual host model for verilog

BaseJump STL: A Standard Template Library for SystemVerilog

A CPU that implementing THCO-MIPS16 instruction set.

Bus bridges and other odds and ends

Test automation standard engineering project template

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

一步一步写MIPS CPU

HDL symbol generator

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

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A Compiler for the Popr Language

💼 É dev? É devops? É bom? Quer mexer com muita tecnologia e desafios? Vem pro match!

Verilog SDRAM memory controller

😱 Falsehoods Programmers Believe in

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

Verilog (SystemVerilog) coding style

Recipe for FPGA cooking

Transmits AM radio on computers without radio transmitting hardware.

Hardware implementation of the SHA-256 cryptographic hash function

Liatrio's DevOps Bootcamp

Open source software for chip reverse engineering.

The OpenPiton Platform

SystemVerilog to Verilog conversion

Reverse shell and rootkit

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Accumulated knowledge and experience in the field of Data Engineering

SystemVerilog compiler and language services

A curated list of awesome engineering blogs, handbooks and open source repos from top technology companies

Chisel 3: A Modern Hardware Design Language

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Hitman Blood Money Reverse Project

All open source file and project for OpenFPGAduino project

a reverse TCP tunnel let you access target behind NAT or firewall

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

LicheeTang 蜂鸟E203 Core

OpenROAD's unified application implementing an RTL-to-GDS Flow

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Certificates of Qualification in Software Engineering

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A practical starting point for designing and building large-scale web frontends.

Virtio implementation in SystemVerilog

Source codes for HHO paper: Harris hawks optimization: Algorithm and applications: https://www.sciencedirect.com/science/article/pii/S0167739X18313530. In this paper, a novel population-based, nature-inspired optimization paradigm is proposed, which is called Harris Hawks Optimizer (HHO).

My personal website & blog

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

A (very) minimal web browser for FPGAs implemented in Verilog

a programmable cryptographic coprocessor in verilog

Dontbug is a reverse debugger for PHP