179 Open source projects that are alternatives of or similar to Meta Riscv

SweRV EL2 Core

FPGA-based RISC-V CPU+SoC.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Maxine VM: A meta-circular research VM

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

SweRV EH1 core

A self-hosting and educational C compiler

Shakti: development platform for PlatformIO

Yet another toy CPU.

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

Nuclei Microcontroller Software Interface Standard Development Repo

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Nuclei RISC-V Software Development Kit

RARS -- RISC-V Assembler and Runtime Simulator

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

MDEPX — A BSD-style RTOS

Yet Another RISC-V Implementation

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

RISC-V Assembler and Runtime Simulator

F# RISC-V Instruction Set formal specification

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

RISC-V Instruction Set Metadata

RISC-V processor emulator written in Rust+WASM

RISC-V RV32I[MAC] emulator with ELF support

Sedna - a pure Java RISC-V emulator.

⛔ DEPRECATED ⛔ HERO Software Development Kit

Simple risc-v emulator, able to run linux, written in C.

A RISC-V simulator

ARV: Asynchronous RISC-V Go High-level Functional Model

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

Renode - Antmicro's virtual development framework for complex embedded systems

Riscy Processors - Open-Sourced RISC-V Processors

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

RISC-V simulator for x86-64

riscv资料、论文等

FPGA 101 - Workshop materials

RISC-V Cores, SoC platforms and SoCs

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

MicroPython for K210 RISC-V, let's play with edge AI easier

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

Tests for example Rocket Custom Coprocessors

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

RISC-V Instruction Set Simulator (Built for education).

A FPGA friendly 32 bit RISC-V CPU implementation

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

v3.5 https://rcore-os.github.io/rCore-Tutorial-Book-v3/

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Featherweight RISC-V implementation

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

The RISC-V software tools list, as seen on riscv.org

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

Alphanumeric+1 shellcoding tools for RISC-V

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

Reko is a binary decompiler.