458 Open source projects that are alternatives of or similar to Plutosdr Fw

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

DDC/DUC SDR Tranceiver project

Notes on the Red Pitaya Open Source Instrument

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

FPGA/hardware design of openwifi

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

The USRP™ Hardware Driver Repository

Stochastic Delta Rule implemented in Pytorch on DenseNet

Rdio Scanner is an interface similar to a police radio scanner for software defined radio recorders

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

VDL Mode 2 message decoder and protocol analyzer

All open source file and project for OpenFPGAduino project

Software Defined Radio Demodulation and Decoding Tools

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Compact FPGA game console

Obtain power spectrum from SoapySDR devices (RTL-SDR, Airspy, SDRplay, HackRF, bladeRF, USRP, LimeSDR, etc.)

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

LicheeTang 蜂鸟E203 Core

Awesome-Cellular-Hacking

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

FPGA-based RISC-V CPU+SoC.

i8080 precise replica in Verilog, based on reverse engineering of real die

Open Source LTE platform - Aims to be an Open Source Software Defined Radio (SDR) Erlang and C++ implementation of the 3GPP release 10 LTE spec

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

📡 On-off keying tools for your SD-arrrR

Scots Army Knife for electronics

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

GPGPU microprocessor architecture

Build Customized FPGA Implementations for Vivado

SystemRDL 2.0 language compiler front-end

a simple and cheap vector network analyzer, including support software

A Video display simulator

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Readsb is a Mode-S/ADSB/TIS decoder for RTLSDR, BladeRF, Modes-Beast and GNS5894 devices.

Connectal is a framework for software-driven hardware development.

An open source 3GPP LTE implementation.

Software defined radio receiver powered by GNU Radio and Qt.

SweRV EL2 Core

A frequency scanner for Gqrx Software Defined Radio receiver

First SDR platform for IoT networks

A simple, basic, formally verified UART controller

An Open Source Deep Learning Inference Engine Based on FPGA

Radio signal analyser

CentSDR: tiny handheld standalone software defined receiver with LCD display.

The Antikernel operating system project

Space Invaders game implemented with VHDL

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Implementations of the Simon and Speck Block Ciphers

📶 1090ES ADS-B Out Add-on

A utility for Composing FPGA designs from Peripherals

A GNU Radio implementation of HD Radio (NRSC-5)

Example designs showing different ways to use SymbiFlow toolchains.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

GNU Radio Android Toolchain