180 Open source projects that are alternatives of or similar to Riscv Boom

Quasar 2.0: Chisel equivalent of SweRV-EL2

Rocket Chip Generator

SoC based on VexRiscv and ICE40 UP5K

FPGA-based RISC-V CPU+SoC.

Simple RISC-V 3-stage Pipeline in Chisel

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SweRV EH1 core

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SweRV EL2 Core

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Imitate SDcard using FPGAs.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Test suite designed to check compliance with the SystemVerilog standard.

Haskell library for hardware description

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

xv6-riscv like OS written in Rust

Odoo (OpenERP) Right to left support for User Interface, report and frontend

ViewPager with RTL support 🔄

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

Chisel Things for OFDM

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

RISC-V processor emulator written in Rust+WASM

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

Nuclei Microcontroller Software Interface Standard Development Repo

A library which configures a divider for a RecyclerView.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

🌍 Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

RISC-V Assembler and Runtime Simulator

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Understanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.

An opinionated starter kit with styled-system, graphql-hooks, mobx and nextjs (PWA)

Scala based HDL

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab…

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

⛔ DEPRECATED ⛔ HERO Software Development Kit

A kernel written in Rust

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

Documentatin for YatCPU

👌🏼 CoreUI is free bootstrap admin template. http://coreui.io

RISC-V simulator for x86-64

RARS -- RISC-V Assembler and Runtime Simulator

A self-hosting and educational C compiler

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

OpenROAD's unified application implementing an RTL-to-GDS Flow

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

RISCV SoftCPU Contest 2018