Chisel3Chisel 3: A Modern Hardware Design Language
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Mutual labels: chip-generator, chisel, rtl, chisel3, firrtl, verilog
essenthigh-performance RTL simulator
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Mutual labels: chisel, rtl, firrtl
Rocket ChipRocket Chip Generator
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Mutual labels: chip-generator, chisel, rtl
PyChip-py-hclA Hardware Construct Language
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Mutual labels: rtl, firrtl, verilog
diagrammerProvides dot visualizations of chisel/firrtl circuits
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Mutual labels: chisel, chisel3, firrtl
QuasarQuasar 2.0: Chisel equivalent of SweRV-EL2
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Mutual labels: chisel, rtl, chisel3
tree-core-cpuA series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
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Mutual labels: chisel, rtl
cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
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Mutual labels: rtl, verilog
OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Mutual labels: rtl, verilog
sphinxcontrib-hdl-diagramsSphinx Extension which generates various types of diagrams from Verilog code.
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Mutual labels: rtl, verilog
hdl-toolsFacilitates building open source tools for working with hardware description languages (HDLs)
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Mutual labels: rtl, verilog
SpinalCryptoSpinalHDL - Cryptography libraries
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Mutual labels: rtl, verilog
vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (+108.7%)
Mutual labels: rtl, verilog
tree-core-ideThe next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Stars: ✭ 79 (+243.48%)
Mutual labels: chisel3, verilog
SpinalDevDocker Development Environment for SpinalHDL
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Mutual labels: rtl, verilog
KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
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Mutual labels: chisel, chisel3
virtioVirtio implementation in SystemVerilog
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Mutual labels: rtl, verilog
FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
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Mutual labels: rtl, verilog
Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
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Mutual labels: rtl, verilog
OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
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Mutual labels: rtl, verilog
