855 Open source projects that are alternatives of or similar to Svlint

Simple tool for fixing common misspellings, typos in source code

Stricter Dart analyzer linter settings and best practices.

Rubocop Linter Action: A GitHub Action to run Rubocop against your code!

An attempt to make Unreal Engine 4 projects more consistent

Identify hardcoded secrets and dangerous behaviours

Lint committed files on pre-push 🔬

Linting for your git commit messages

A pluggable and configurable linter tool for identifying and reporting on patterns of misuse or deprecations in Gradle scripts.

🐛 A tool that can speed up linting of php files by running several lint processes at once.

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

A nicer HDL.

Linter plugin for PHP, using PHP_CodeSniffer.

Atom linter plugin for JavaScript, using JavaScript Standard Style

QTools collection of open source tools for embedded systems development on Windows, Linux and MacOS

A reimplementation of a tiny stack CPU

Kubernetes object analysis with recommendations for improved reliability and security

git commit message linter hook

High throughput JPEG decoder in Verilog for FPGA

Lightning fast concurrent PHP linter for Node.js, Grunt & Gulp! ⚡️

Linter for the Nix expression language

Light-weight RISC-V RV32IMC microcontroller core.

Github app to validate commit message on a pull request

The official GitHub mirror of https://gitlab.com/pycqa/flake8

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

IC design and development should be faster，simpler and more reliable

X.509 certificate linter, written in Go

CDBUS Protocol and the IP Core for FPGA users

A Video display simulator

Bitcoin miner for Xilinx FPGAs

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

This is the main repository for all the examples for the book Practical UVM

🍭 Boilerplate for ES6+ Node.js and npm Developer

Proselint wrapper with a friendly reporter

Dockerfile linter, written in Golang 🐳

A (WIP) Extremely fast JavaScript and TypeScript linter and Rust crate

Linting your CSS to limit yourself to a defined subset of values.

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

A linter for Clojure code that sparks joy.

Formats GraphQL schema definition language (SDL) document.

A single-wire bi-directional chip-to-chip interface for FPGAs

FPGA 101 - Workshop materials

Code generation tool for configuration and status registers

A very primitive but hopefully self-educational CPU in Verilog

A mixed signal netlist language (pre-alpha)

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Homotopy theory in Coq.

A RuboCop configuration focusing Lint. Recommended by Sider

A small 6502 system with MS BASIC in ROM

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

Ham Radio hat for Raspberry PI

FPGA-based C64 Accelerator / C65 like computer

A wishbone controlled scope for FPGA's

A FPGA friendly 32 bit RISC-V CPU implementation

ESLint Shareable Config for JSX support in JavaScript Standard Style

RTL, Cmodel, and testbench for NVDLA

Compact FPGA game console

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT