118 Open source projects that are alternatives of or similar to vega-lite

RISC-V Cores, SoC platforms and SoCs

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

🖥️ An xv6-like operating system on RISC-V with multi-core support. Documentation available online.

RISC-V instruction set simulator built for education

Where Lions Roam: RISC-V on the VELDT

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

C++17 RISC-V RV32GC / RV64GC userspace emulator library

bl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706, BL616/BL618, BL808 and other series of RISC-V based chips in the future.

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

BL602 SDK. Any technical topic, please access the following link.

FPGA-based RISC-V CPU+SoC.

Simple and lightweight source-based multi-platform Linux distribution with musl libc.

32-bit Superscalar RISC-V CPU

F# RISC-V Instruction Set formal specification

Bare-metal Forth implementation for RISC-V

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

ARMv8-A/RISC-V kernel (with UEFI bootloader)

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

Nuclei RISC-V Software Development Kit

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

A port of FreeRTOS for the RISC-V ISA

SweRV EL2 Core

A toy operating system written in Rust on RISC V(rv32im)

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

Kendryte K210: development platform for PlatformIO

MicroPython for K210 RISC-V, let's play with edge AI easier

Mirror; Work-in-progress software-rendering Vulkan implementation

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Linear algebra accelerators for RISC-V (published in ICCD 17)

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A simple RISC-V processor for use in FPGA designs.

No-MMU Linux capable RISC-V SoC designed to be useful.

RISC-V CPU Core

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

GD32V: development platform for PlatformIO

Tiny RISC-V virtual machine

LicheeTang 蜂鸟E203 Core

9444 RISC-V 64IMA CPU and related tools and peripherals.

All CPU and MCU documentation in one place

RISC-V Instruction Set Metadata

OpenEmbedded/Yocto layer for RISC-V Architecture

R3-OS — Experimental static (μITRON-esque) RTOS for deeply embedded systems, testing the limit of Rust's const eval and generics

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Functional verification project for the CORE-V family of RISC-V cores.

v3.5 https://rcore-os.github.io/rCore-Tutorial-Book-v3/

Simple 3-stage pipeline RISC-V processor

Compact FPGA game console

Universal Cooperative Multithread Lib with real time Scheduler that was designed to work, virtually, into any modern micro controller or Microchip and, also, for user space applications for modern OS (Mac, Linux, Windows) or on FreeRTOS as well. Supports C and C++

RISC-V Instruction Set Simulator (Built for education).

Extendable Translating Instruction Set Simulator

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

Shakti: development platform for PlatformIO

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

This is the main repo for Penglai.

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Yet another toy CPU.

RISC-V Software Simulation

MultiZone® Security Enclave for Linux

Processor core implementing the base RV32I instruction set of the RISC-V ISA

为推广RISC-V尽些薄力