Top 3 openram open source projects

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

✭ 1,765

python shell Makefile magic eda asic pdk asic-library openroad openram skywater

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

✭ 130

Verilog shell tcl Makefile python c magic yosys caravel picorv32 openroad openram sky130

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

✭ 548

Verilog python tcl Dockerfile shell Makefile magic asic rtl verilog vlsi foundry fault yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds qflow

1-3 of 3 openram projects