Top 9 yosys open source projects

caravel mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
cariboulite
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
formal hw verification
Trying to verify Verilog/VHDL designs with formal methods and tools
yosys
Unofficial Yosys WebAssembly packages
padring
A padring generator for ASICs
1-9 of 9 yosys projects