Top 7 vlsi open source projects

VLSI EDA Global Router

✭ 35

C++c shell router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

act

ACT hardware description language and core tools.

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

✭ 548

Verilog python tcl Dockerfile shell Makefile magic asic rtl verilog vlsi foundry fault yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds qflow

AMC

AMC: Asynchronous Memory Compiler

✭ 31

python HCL AMPL SourcePawn c TeX eda vlsi design-automation asynchronous-vlsi asynchronous-sram

DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

✭ 54

Verilog python verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

✭ 49

Verilog C++Coq verilog vlsi atalanta atpg

padring

A padring generator for ASICs

✭ 19

C++CMake asic eda chip vlsi yosys

1-7 of 7 vlsi projects