GitPlanet

Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details
All Projects → ZipCPU → openarty

ZipCPU / openarty

Licence: other
An Open Source configuration of the Arty platform

Programming Languages

Verilog
626 projects
C++
36643 projects - #6 most used programming language
Coq
218 projects
c
50402 projects - #5 most used programming language
Makefile
30231 projects
shell
77523 projects

Labels

fpgafpga-socwishboneverilatorartyzipcpuwishbone-bus

Projects that are alternatives of or similar to openarty

s6soc
CMod-S6 SoC
Stars: ✭ 30 (-67.74%)
Mutual labels:  fpga, fpga-soc, wishbone, verilator, zipcpu, wishbone-bus
wbi2c
Wishbone controlled I2C controllers
Stars: ✭ 25 (-73.12%)
Mutual labels:  fpga, verilator, wishbone-bus
dbgbus
A collection of debugging busses developed and presented at zipcpu.com
Stars: ✭ 24 (-74.19%)
Mutual labels:  wishbone, verilator, wishbone-bus
yarvi
Yet Another RISC-V Implementation
Stars: ✭ 59 (-36.56%)
Mutual labels:  fpga, fpga-soc
dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
Stars: ✭ 147 (+58.06%)
Mutual labels:  fpga, verilator
dpll
A collection of phase locked loop (PLL) related projects
Stars: ✭ 55 (-40.86%)
Mutual labels:  fpga, verilator
HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
Stars: ✭ 27 (-70.97%)
Mutual labels:  fpga, fpga-soc
virtio
Virtio implementation in SystemVerilog
Stars: ✭ 38 (-59.14%)
Mutual labels:  fpga, verilator
tapasco
The Task Parallel System Composer (TaPaSCo)
Stars: ✭ 66 (-29.03%)
Mutual labels:  fpga, fpga-soc
TinyMIPS
The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.
Stars: ✭ 29 (-68.82%)
Mutual labels:  fpga, fpga-soc
fmh gpib core
GPIB IEEE 488.1 core
Stars: ✭ 15 (-83.87%)
Mutual labels:  fpga, fpga-soc
rodinia
AGM bitstream utilities and decoded files from Supra
Stars: ✭ 21 (-77.42%)
Mutual labels:  fpga
dcurl
Hardware-accelerated Multi-threaded IOTA PoW, drop-in replacement for ccurl
Stars: ✭ 39 (-58.06%)
Mutual labels:  fpga
adat-usb2-audio-interface
FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs
Stars: ✭ 68 (-26.88%)
Mutual labels:  fpga
ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
Stars: ✭ 144 (+54.84%)
Mutual labels:  fpga
FpOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
Stars: ✭ 138 (+48.39%)
Mutual labels:  fpga
gateware
A collection of little open source FPGA hobby projects
Stars: ✭ 38 (-59.14%)
Mutual labels:  fpga
risc8
Mostly AVR compatible FPGA soft-core
Stars: ✭ 19 (-79.57%)
Mutual labels:  fpga
ice-chips-verilog
IceChips is a library of all common discrete logic devices in Verilog
Stars: ✭ 78 (-16.13%)
Mutual labels:  fpga
EDSAC
FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
Stars: ✭ 28 (-69.89%)
Mutual labels:  fpga
View All Similar Projects ➔

Description

The purpose of the OpenArty project is to implement a ZipCPU on an Arty platform, together with open source drivers for all of the Arty peripherals. In my case, that will include drivers for additional PMods that I have purchased for the project. Hence the OpenArty platform with support:

  1. Generic flash driver, to include access to all of the flash's functionality such as being able to read its ID as well as being able to read and set the one time programmable memory. This in addition to being flash manufacturer agnostic. Further, when complete, a ZipCPU will launch code automatically from the flash on startup.
  2. DDR3 SDRAM (Done)
  3. The Internal Configuration Access Port (ICAPE2), to allow for dynamic (not partial) reconfiguration (Done)
  4. Ethernet (Done)
  5. SD Card. The program currently uses the SDSPI controller, although I intend to upgrade to a full SDIO controller with (hopefully) the same identical or nearly identical interface.
  6. OLEDrgb display. (Done)
  7. GPS clock module, and external USB-UART. (Done)
  8. This leaves one open PMOD port which ... I haven't decided what to connect it to.

As a demonstration project, I'd love to implement an NTP server within the device. This is a long term goal, however, and a lot needs to be accomplished before I can get there. Still, a $130 NTP server isn't a bad price for an NTP server in your lab. ($99 for the Arty, $25 for the GPS receiver IIRC)

Current Status

This version of the OpenArty project is built around AutoFPGA. It is designed to be highly reconfigurable, so that you can add (or remove) peripherals quickly and easily. My specific goal is to use AutoFPGA to create a project that doesn't require all of the peripherals I've used, but may be instead built with only those peripherals on the board.

Repository

Due to the ongoing issues with OpenCores, the official OpenArty repository is being kept on GitHub, under the ZipCPU username.

License

Gisselquist Technology, LLC, is pleased to provide you with this entire OpenArty project under the GPLv3 license. If this doesn't work for you, please feel free to contact me.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].