Pynq DlXilinx Deep Learning IP
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Sublime VhdlVHDL Package for Sublime Text
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FpgbaGBA on FPGA
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Freezing SpiceA pipelined RISCV implementation in VHDL
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VhdlVHDL Samples
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YafcYet Another Forth Core...
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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Ethernet macTri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
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OphidianOphidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
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Hdl4fpgaVHDL library 4 FPGAs
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PatmosPatmos is a time-predictable VLIW processor, and the processor for the T-CREST project
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Vna2Second version of homemade 30 MHz - 6 GHz VNA
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NeppielightFPGA-based HDMI ambient lighting
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PotatoA simple RISC-V processor for use in FPGA designs.
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Aws FpgaOfficial repository of the AWS EC2 FPGA Hardware and Software Development Kit
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Nexys4ddrVarious projects for the Nexys4DDR board from Digilent
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Fpga FftA highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
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Vhdl libLibrary of VHDL components that are useful in larger designs.
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Open Source Fpga Bitcoin MinerA completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
Stars: ✭ 989 (+394.5%)
Xjtu TriplerThis repository is the backup of XJTU-Tripler project, participating dac19 system design contest
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Vhdl ModeA package for Sublime Text that aids coding in the VHDL language.
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Fmcw3Two RX-channel 6 GHz FMCW radar design files
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TpuTPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
Stars: ✭ 91 (-54.5%)
TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
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GhdlVHDL 2008/93/87 simulator
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Neo430A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
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GretaGRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.
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UvvmUVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
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ZynqbtcA Bitcoin miner for the Zynq chip utilizing the Zedboard.
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ZpuThe Zylin ZPU
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FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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J1scA reimplementation of a tiny stack CPU
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Artix 7 Hdmi ProcessingReceiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
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Q2727-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
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Haddoc2Caffe to VHDL
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Cosmos Plus OpenssdCosmos OpenSSD + Hardware and Software source distribution
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Spi FpgaSPI master and slave for FPGA written in VHDL
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OsvvmOSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
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ReonvReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
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ScaffoldDonjon hardware tool for circuits security evaluation
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DegateOpen source software for chip reverse engineering.
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Hdl checkerRepurposing existing HDL tools to help writing better code
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FlearadioDigital FM Radio Receiver for FPGA
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Bladerf WiphybladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
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Fpga displayportAn implementation of DisplayPort protocol for FPGAs
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Hardh264A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
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YodlA VHDL frontend for Yosys
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