93 Open source projects that are alternatives of or similar to Cv32e40p

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

异步内核就像风一样快！

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

MDEPX — A BSD-style RTOS

SoC based on VexRiscv and ICE40 UP5K

xv6-riscv like OS written in Rust

Sedna - a pure Java RISC-V emulator.

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Jonesforth RISC-V port.

Documentatin for YatCPU

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

Nuclei Microcontroller Software Interface Standard Development Repo

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

pulp_soc is the core building component of PULP based SoCs

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Yet Another RISC-V Implementation

SweRV EH1 core

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

⛔ DEPRECATED ⛔ HERO Software Development Kit

Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.

A self-hosting and educational C compiler

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

RISC-V SystemC-TLM simulator

Freedom U Software Development Kit (FUSDK)

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

ARV: Asynchronous RISC-V Go High-level Functional Model

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

The Gee (寂) Operating System, written in YuLang.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

RISC-V RV32I[MAC] emulator with ELF support

RARS -- RISC-V Assembler and Runtime Simulator

Simple risc-v emulator, able to run linux, written in C.

Quasar 2.0: Chisel equivalent of SweRV-EL2

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

RISC-V Assembler and Runtime Simulator

A RISC-V simulator

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Yet another toy CPU.

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

Nuclei RISC-V Software Development Kit

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

UNIX-like operating system written in C and C++

A kernel written in Rust

bl602 serial flasher

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

This repo contains the artifact for our SOSP'19 paper on Serval

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

RISC-V Instruction Set Metadata

Maxine VM: A meta-circular research VM

RISCV SoftCPU Contest 2018

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

RISC-V processor emulator written in Rust+WASM

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP