362 Open source projects that are alternatives of or similar to dbgbus

CMod-S6 SoC

Wishbone controlled I2C controllers

An Open Source configuration of the Arty platform

Bazel build rules for Verilator

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Virtio implementation in SystemVerilog

Facilitates building open source tools for working with hardware description languages (HDLs)

Virtual development board for HDL design

A configurable C++ generator of pipelined Verilog FFT cores

A collection of phase locked loop (PLL) related projects

Recipe for FPGA cooking

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

A High-performance Timing Analysis Tool for VLSI Systems

Hardware implementation of the SHA-256 cryptographic hash function

BaseJump STL: A Standard Template Library for SystemVerilog

Open source software for chip reverse engineering.

SystemVerilog to Verilog conversion

Bus bridges and other odds and ends

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

SystemVerilog compiler and language services

CNN acceleration on virtex-7 FPGA with verilog HDL

Small footprint and configurable PCIe core

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Chisel 3: A Modern Hardware Design Language

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

CHIP-8 console on FPGA

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

FPGA,Verilog,Python

synthesiseable ieee 754 floating point library in verilog

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Verilog Generator of Neural Net Digit Detector for FPGA

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

A litecoin scrypt miner implemented with FPGA on-chip memory.

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

FPGA/hardware design of openwifi

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Repository for the SCALE-MAMBA MPC system

The USRP™ Hardware Driver FPGA Repository

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Must-have verilog systemverilog modules

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Verilog UART

32-bit Superscalar RISC-V CPU

iCESugar FPGA Board (base on iCE40UP5k)

一步一步写MIPS CPU

All open source file and project for OpenFPGAduino project

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Open source design files for the TinyFPGA B-Series boards.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

An open source SPI flash emulator and monitor

Notes on the Red Pitaya Open Source Instrument

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

LicheeTang 蜂鸟E203 Core

A simple, basic, formally verified UART controller

Verilog I2C interface for FPGA implementation

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

🌱 ❄️ Collection of open-source peripherals in Verilog