Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
Stars: ✭ 2,257 (+1146.96%)
Beagle sdr gpsKiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
Stars: ✭ 300 (+65.75%)
oscimpDigitalOscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
Stars: ✭ 41 (-77.35%)
Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
Stars: ✭ 205 (+13.26%)
hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (-19.89%)
1bitSDRMinimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
Stars: ✭ 53 (-70.72%)
UhdThe USRP™ Hardware Driver Repository
Stars: ✭ 544 (+200.55%)
TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
Stars: ✭ 153 (-15.47%)
Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+429.28%)
Higan VerilogThis is a higan/Verilator co-simulation example/framework
Stars: ✭ 35 (-80.66%)
Gnss SdrGNSS-SDR, an open-source software-defined GNSS receiver
Stars: ✭ 801 (+342.54%)
OpenwebrxOpen source, multi-user SDR receiver software with a web interface
Stars: ✭ 813 (+349.17%)
Fpga Chip8CHIP-8 console on FPGA
Stars: ✭ 169 (-6.63%)
IrohaIntermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Stars: ✭ 30 (-83.43%)
WbscopeA wishbone controlled scope for FPGA's
Stars: ✭ 50 (-72.38%)
VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+475.14%)
ElectronA mixed signal netlist language (pre-alpha)
Stars: ✭ 52 (-71.27%)
Halide HlsHLS branch of Halide
Stars: ✭ 59 (-67.4%)
Mips CpuA MIPS CPU implemented in Verilog
Stars: ✭ 38 (-79.01%)
RggenCode generation tool for configuration and status registers
Stars: ✭ 54 (-70.17%)
PysdrA guide for using Python as a software-defined radio (SDR) framework, for extremely rapid development of SDR apps/research with beautiful GUIs
Stars: ✭ 60 (-66.85%)
Core jpegHigh throughput JPEG decoder in Verilog for FPGA
Stars: ✭ 64 (-64.64%)
TinysdrFirst SDR platform for IoT networks
Stars: ✭ 78 (-56.91%)
Ustc RvsocFPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-57.46%)
PagermonMultimon-ng pager message parser and viewer
Stars: ✭ 154 (-14.92%)
PipecnnAn OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Stars: ✭ 775 (+328.18%)
ZbasicA bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Stars: ✭ 27 (-85.08%)
HdlHDL libraries and projects
Stars: ✭ 727 (+301.66%)
Icestudio❄️ Visual editor for open FPGA boards
Stars: ✭ 958 (+429.28%)
Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
Stars: ✭ 31 (-82.87%)
SpinalhdlScala based HDL
Stars: ✭ 696 (+284.53%)
LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Stars: ✭ 149 (-17.68%)
Hrm CpuHuman Resource Machine - CPU Design #HRM
Stars: ✭ 43 (-76.24%)
Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+486.74%)
Rsyocto🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
Stars: ✭ 41 (-77.35%)
Airspy FmradionSoftware decoder for FM/AM broadcast radio with AirSpy R2 / Mini, Airspy HF+, and RTL-SDR
Stars: ✭ 59 (-67.4%)
QspectrumanalyzerSpectrum analyzer for multiple SDR platforms (PyQtGraph based GUI for soapy_power, hackrf_sweep, rtl_power, rx_power and other backends)
Stars: ✭ 677 (+274.03%)
Dumpvdl2VDL Mode 2 message decoder and protocol analyzer
Stars: ✭ 100 (-44.75%)
CentsdrCentSDR: tiny handheld standalone software defined receiver with LCD display.
Stars: ✭ 76 (-58.01%)
AntikernelThe Antikernel operating system project
Stars: ✭ 75 (-58.56%)
Soapy powerObtain power spectrum from SoapySDR devices (RTL-SDR, Airspy, SDRplay, HackRF, bladeRF, USRP, LimeSDR, etc.)
Stars: ✭ 88 (-51.38%)
Symbiflow ExamplesExample designs showing different ways to use SymbiFlow toolchains.
Stars: ✭ 71 (-60.77%)
NyuziprocessorGPGPU microprocessor architecture
Stars: ✭ 1,351 (+646.41%)
Pp4fpgas Cn HlsHLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
Stars: ✭ 97 (-46.41%)
Jt gngCAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.
Stars: ✭ 65 (-64.09%)
LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Stars: ✭ 110 (-39.23%)
VgasimA Video display simulator
Stars: ✭ 94 (-48.07%)
AutofpgaA utility for Composing FPGA designs from Peripherals
Stars: ✭ 108 (-40.33%)
Vm80ai8080 precise replica in Verilog, based on reverse engineering of real die
Stars: ✭ 114 (-37.02%)
Gemm hlsScalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Stars: ✭ 134 (-25.97%)
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Stars: ✭ 131 (-27.62%)
Wbuart32A simple, basic, formally verified UART controller
Stars: ✭ 133 (-26.52%)
Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
Stars: ✭ 126 (-30.39%)
Symbiflow Arch DefsFOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Stars: ✭ 137 (-24.31%)
Wb2axipBus bridges and other odds and ends
Stars: ✭ 177 (-2.21%)