681 Open source projects that are alternatives of or similar to R8051

32-bit Superscalar RISC-V CPU

A MIPS CPU implemented in Verilog

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

L1VM - a tiny virtual machine with a 64 bit core

Human Resource Machine - CPU Design #HRM

tiny fast portable real-time deep neural network for regression and classification within 50 LOC.

FPGA-based RISC-V CPU+SoC.

A 8-bit computer made of 74xx series logic gates and memory ICs.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A small, light weight, RISC CPU soft core

A reimplementation of a tiny stack CPU

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

TIC-80 is a fantasy computer for making, playing and sharing tiny games.

RISC-V CPU Core (RV32IM)

A FPGA friendly 32 bit RISC-V CPU implementation

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Single header Z80 emulator for C++ (C++11 or later)

8 bit-ish style post-processing effect for Unity

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Reads a state transition system and performs property checking

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Revengineered ancient PDP-11 CPUs, originals and clones

Standard Cell Library based Memory Compiler using FF/Latch cells

Single-purpose tools to stress resources

CPU 内存（Memory）Network FPS 实时监测 查看沙盒sandbox

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

🍵 Tiny, easy and powerful React state management

A JavaScript simulator to demonstrate the front panel operations of Altair 8800.

Real-time software rasterizer written in C++ with windowing and model loading support.

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

NES emulator in Rust with GUI

Trying to verify Verilog/VHDL designs with formal methods and tools

An Understandable 6502 Emulator

Show Me A Graph - Command Line Graphing

Otus Lisp (Ol in short) is a purely* functional dialect of Lisp.

Tiny unzip helper class for .NET 3.5 Client Profile and Mono 2.10, written in pure C#.

A tiny utility to colorize stdin/stdout

8x8 monochrome bitmap fonts for rendering. Implemented in Rust.

Unifying Python/C++/CUDA memory: Python buffered array ↔️ `std::vector` ↔️ CUDA managed memory

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

x86 JIT compiler in 86 lines

Commodore 16 schematics and PCB, redrawn in Kicad

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

This is a repository for a No-Code object detection inference API using the OpenVINO. It's supported on both Windows and Linux Operating systems.

My solutions to the NAND-to-CPU game MHRD

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Nim utilities for advanced CPU operations: CPU identification, ISA extension detection, bindings to assorted intrinsics

Yet Another RISC-V Implementation

a tiny downloader with console panel.

🔬 dd's x86 CPU Identification tool

A tiled DeepDream project for creating any size of image, on both CPU and GPU

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

tiny Zig allocator primarily targeting WebAssembly

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

BetterC CPU Identification Routines

GORILLA.BAS port to CP/M in Turbo Modula-2. Supported terminals: VT52, VT100, ANSI, ADM-31, KayPro, C128, Memotech monochrome, CPC / Zenith Z19