130 Open source projects that are alternatives of or similar to rc-fpga-zcu

Yet another toy CPU.

MultiZone® Security Enclave for Linux

RISC-V RV32I[MAC] emulator with ELF support

Yet Another RISC-V Implementation

This is the main repo for Penglai.

A low cost FPGA development board for absolute newbies

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

List of ideas for getting started with TimVideos projects

9444 RISC-V 64IMA CPU and related tools and peripherals.

Kendryte K210 BSP for RT-Thread

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

RISC-V Cores, SoC platforms and SoCs

🌟 Alhambra II FPGA board

Software, tools, and documentation for RV32-VEGA-Lite platform

⛔ DEPRECATED ⛔ HERO Software Development Kit

R3-OS — Experimental static (μITRON-esque) RTOS for deeply embedded systems, testing the limit of Rust's const eval and generics

ARV: Asynchronous RISC-V Go High-level Functional Model

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Dockerfile with Vivado for CI

BL602 SDK (Pine64 fork)

Simple 3-stage pipeline RISC-V processor

Riscv32 CPU Project

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

Sedna - a pure Java RISC-V emulator.

No-MMU Linux capable RISC-V SoC designed to be useful.

QEMU platform SBI support implementation, using RustSBI

A RISC-V simulator

Global Dark Mode for ALL apps on ANY platforms.

Interesting project，the Fast Real Time Operating Systems( FOS-RTOS)

Lightweight and performant dynamic binary translation for RISC–V code on x86–64

Low-cost ECP5 FPGA development board

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

DMA source and sink blocks for Xilinx Zynq FPGAs

Multi-Platform C code Library for EVE graphics controllers from FTDI / Bridgetek (FT810, FT811, FT812, FT813, BT815, BT816, BT817, BT818)

RISC-V Software Simulation

The RISC-V software tools list, as seen on riscv.org

Nuclei RISC-V Software Development Kit

MDEPX — A BSD-style RTOS

Extendable Translating Instruction Set Simulator

A simple three-stage RISC-V CPU

Linear algebra accelerators for RISC-V (published in ICCD 17)

This tutorial provides one example on how a CI (Continuous Integration) workflow with the IAR Build Tools for Linux can be set up on GitHub. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

Bare-metal Forth implementation for RISC-V

Let's write an OS which can run on RISC-V in Rust from scratch!

bl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706, BL616/BL618, BL808 and other series of RISC-V based chips in the future.

Fast constant-time AES implementations on 32-bit architectures

A toy operating system written in Rust on RISC V(rv32im)

Homebrew game for homebrew FPGA game console

Processor core implementing the base RV32I instruction set of the RISC-V ISA

Simple risc-v emulator, able to run linux, written in C.

Virtio implementation in SystemVerilog

hub.docker.com/repository/docker/davidburela/riscv-emulator

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

A RISC-V 32bit single-cycle CPU written in Logisim

A 32-bit RISC-V emulator in a shader (and C)

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Evaluation board for AllWinner's RISC-V 64 SoC F133/D1s