93 Open source projects that are alternatives of or similar to Rocket Rocc Examples

RISC-V SystemC-TLM simulator

Simple risc-v emulator, able to run linux, written in C.

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

Yet another toy CPU.

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

The Gee (寂) Operating System, written in YuLang.

RARS -- RISC-V Assembler and Runtime Simulator

A RISC-V simulator

Quasar 2.0: Chisel equivalent of SweRV-EL2

A kernel written in Rust

UNIX-like operating system written in C and C++

RISC-V Assembler and Runtime Simulator

RISCV SoftCPU Contest 2018

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

ARV: Asynchronous RISC-V Go High-level Functional Model

Maxine VM: A meta-circular research VM

RISC-V RV32I[MAC] emulator with ELF support

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Nuclei RISC-V Software Development Kit

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

⛔ DEPRECATED ⛔ HERO Software Development Kit

Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Documentatin for YatCPU

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

SonicBOOM: The Berkeley Out-of-Order Machine

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A self-hosting and educational C compiler

MDEPX — A BSD-style RTOS

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

RISC-V processor emulator written in Rust+WASM

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

A FPGA friendly 32 bit RISC-V CPU implementation

pulp_soc is the core building component of PULP based SoCs

Nuclei Microcontroller Software Interface Standard Development Repo

Sedna - a pure Java RISC-V emulator.

SweRV EH1 core

Yet Another RISC-V Implementation

xv6-riscv like OS written in Rust

异步内核就像风一样快！

RISC-V simulator for x86-64

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Jonesforth RISC-V port.

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining