105 Open source projects that are alternatives of or similar to rustsbi

QEMU platform SBI support implementation, using RustSBI

Reimplementation of the Nintendo Switch firmware

UNIX-like operating system written in C and C++

RISC-V Instruction Set Metadata

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

bxCAN peripheral driver for STM32 chips

SoC based on VexRiscv and ICE40 UP5K

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Embedded Rust's Peripheral Access Crate for BL602 microcontrollers

VSCode debug extension for probe-rs. It uses the MS DAP protocol to communicate directly with the probe (via probe-rs), and supports basic command line debugging in addition to VSCode UI.

异步内核就像风一样快！

MDEPX — A BSD-style RTOS

Jonesforth RISC-V port.

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

A toy operating system written in Rust on RISC V(rv32im)

RISC-V RV32I[MAC] emulator with ELF support

This repo contains the artifact for our SOSP'19 paper on Serval

⛔ DEPRECATED ⛔ HERO Software Development Kit

Serialize & deserialize device tree binary using serde

Simple risc-v emulator, able to run linux, written in C.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

RISC-V SystemC-TLM simulator

A RISC-V simulator

CKB's vm, based on open source RISC-V ISA

F# RISC-V Instruction Set formal specification

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

ARV: Asynchronous RISC-V Go High-level Functional Model

Yet another toy CPU.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

Nuclei RISC-V Software Development Kit

The Gee (寂) Operating System, written in YuLang.

Firmware and software for the Sinara Stabilizer module with high speed, low latency ADC/DAC data processing and powerful DSP algorithms in between

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

bl602 serial flasher

RISCV SoftCPU Contest 2018

Rust support for the Teensy 4

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

ChibiOS for Rust

Freedom U Software Development Kit (FUSDK)

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

pulp_soc is the core building component of PULP based SoCs

Shakti: development platform for PlatformIO

A kernel written in Rust

Simple RISC-V 3-stage Pipeline in Chisel

Sedna - a pure Java RISC-V emulator.

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

[WIP] embedded-hal for the STM32WB family of microcontrollers

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

Implementation of bluetooth-hci for STM32WB5x wireless SoC

Documentatin for YatCPU

Learning embedded development with Rust on the micro:bit

Yet Another RISC-V Implementation