All Git Users → chipsalliance

15 open source projects by chipsalliance

[ Open user page on Github ]

1. Rocket Chip

Rocket Chip Generator

✭ 2,079

scala C++python Verilog shell Makefile assembly rtl riscv rocket-chip chip-generator chisel

2. Chisel3

Chisel 3: A Modern Hardware Design Language

✭ 2,290

scala verilog rtl chip-generator chisel chisel3 firrtl

3. Cores Swervolf

FuseSoC-based SoC for SweRV EH1

✭ 92

tools verilog

4. Dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

✭ 89

5. Cores Swerv El2

SweRV EL2 Core

✭ 79

fpga risc-v rtl riscv processor

6. Omnixtend

OmniXtend cache coherence protocol

✭ 49

tex

7. Cores Swerv

SweRV EH1 core

✭ 406

fpga risc-v rtl riscv processor

8. Firrtl

Flexible Intermediate Representation for RTL

✭ 393

scala compiler hardware

9. sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

✭ 148

SystemVerilog python javascript CSS HTML Makefile rtl verilog hdl compliance-testing symbiflow

10. treadle

Chisel/Firrtl execution engine

✭ 122

scala

11. SweRV-ISS

No description, website, or topics provided.

✭ 57

C++c Makefile HTML

12. rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

✭ 32

shell

13. Cores-SweRV fpga

No description, website, or topics provided.

✭ 31

tcl Verilog c Makefile assembly

14. Cores-SweRV-EH2

No description, website, or topics provided.

✭ 168

SystemVerilog c perl Verilog assembly C++

15. aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

✭ 106

Verilog SystemVerilog tcl forth c Stata

1-15 of 15 user projects