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Top 11 chisel open source projects

Rocket Chip Generator

✭ 2,079

scala C++python Verilog shell Makefile assembly rtl riscv rocket-chip chip-generator chisel

Chisel 3: A Modern Hardware Design Language

✭ 2,290

scala verilog rtl chip-generator chisel chisel3 firrtl

Quasar 2.0: Chisel equivalent of SweRV-EL2

✭ 19

scala SystemVerilog perl c Verilog C++processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Chisel Things for OFDM

✭ 23

scala python C++shell Makefile assembly Verilog chip-generator chisel rtl chisel3 firrtl verilog

Provides dot visualizations of chisel/firrtl circuits

✭ 76

scala shell visualization chisel chisel3 firrtl

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

✭ 68

Verilog scala cpu fpga chisel riscv

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

✭ 37

scala SystemVerilog tcl python assembly Makefile shell fpga intel chisel riscv chisel3 altera risc-v rv32i avalon-mm

high-performance RTL simulator

✭ 60

scala C++shell chisel rtl firrtl

Chisel components for FPGA projects

✭ 88

scala C++tcl Verilog Makefile shell c fpga chisel hardware-libraries

Chisel-FFT-generator

FFT generator using Chisel

✭ 26

Verilog SystemVerilog scala tcl VHDL chisel fft rtl-generator

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

✭ 22

scala shell Makefile python C++Verilog cpu processor chisel riscv rtl rt-thread verilator softcore

1-11 of 11 chisel projects