All Git Users → ultraembedded

6 open source projects by ultraembedded

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32-bit Superscalar RISC-V CPU

✭ 208

linux verilog fpga cpu risc-v asic

High throughput JPEG decoder in Verilog for FPGA

✭ 64

verilog fpga mjpeg

RISC-V CPU Core (RV32IM)

✭ 272

verilog fpga cpu verification risc-v asic

Various HDL (Verilog) IP Cores

✭ 271

audio verilog fpga usb rtl spi asic

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

✭ 190

c Verilog python assembly objective c Makefile fpga mjpeg hdmi sd-card motion-jpeg rtos vga risc-v jpeg-decoder ir-codes artix-7 fpga-media-player hd-video

6. core ddr3 controller

A DDR3 memory controller in Verilog for various FPGAs

✭ 178

Verilog SystemVerilog Makefile

1-6 of 6 user projects