Top 5 ddr open source projects

mirror of https://git.elphel.com/Elphel/eddr3

✭ 33

Verilog SystemVerilog python HCL fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

✭ 53

SystemVerilog c C++tcl Verilog Cuda benchmark fpga ddr hbm

ddal

DDAL(Distributed Data Access Layer) is a simple solution to access database shard.

✭ 33

java mysql converter schema sql ddr transaction shard load-balancer distributed sequence datasource access-database-shard

FPGA ThreeLevelStorage

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

✭ 86

Coq VHDL Verilog c SystemVerilog shell fpga ddr verilog sd-card sdram-controller

my hdmi device

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

✭ 66

GLSL Verilog ddr verilog sdr hdmi dvi vga ice40 icestick icoboard pmod ecp5 ulx3s tmds blackicemx dvi-standard hdmi-device tmds-encoding arty7 sipeed-tang-nano sipeed-tang-nano4k

1-5 of 5 ddr projects