Top 693 tcl open source projects

Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:

Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL

Multi-platform desktop Forth based on Tcl/Tk

Generator of verilog description for FPGA MobileNet implementation

Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs

UCSD Sizer for leakage/dynamic power recovery, timing recovery

Python wrapper for CloudCompare

9444 RISC-V 64IMA CPU and related tools and peripherals.

An implementation of the AWSEM coarse-grained protein folding forcefield in OpenMM

Windows-specific Tcl extension to access and implement COM objects

Parameterized Booth Multiplier in Verilog 2001

clone of miller puckette's puredata

An OpenCL-Based FPGA Accelerator for Compressed YOLOv2

APSIM

东南大学信息学院大三短学期FPGA课程设计——售货机

Tcl client library for Redis

MyCloud插件使用教程

Ansible code for deploying EDB Postgres database clusters and related products.

基于ZYNQ+AD9363的开源SDR硬件

幻影坦克(特指点开后不一样的图片)快速发车工具

Driving the OLED display on the ZedBoard

Macintosh Plus for MiSTer

Parts of my homedir I don't want to be without

Open CASCADE Technology (OCCT), a software development platform providing services for 3D surface and solid modeling

Yet Another Static Site (Generator)

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

django-web for EDP

The semantics of Java in K

FOSS Flow For FPGA

Joe Armstrong implementation of X11 protocol for Erlang

No description, website, or topics provided.

No description, website, or topics provided.

Open Source Relational Database Management System in Python

Residual Binarized Neural Network

A portable, ROM-booting hobby OS. Currently supports m68k, arm, and PowerPC targets

A redis module, similar to redis string, but you can set expire and version for the value. It also provides many very useful commands, such as cas/cad, etc.

Generates Makefiles to synthesize, place, and route verilog using Vivado

Google's TCP BBR implementation for ns2 network simulator

Acorn Archimedes for MiSTer

TEE hardware - based on the chipyard repository - hardware to accelerate TEE

CPU based on MIPS with 5-stage pipeline and cache, working with DDR2 memory and SD card.

Ada-language framework

Fiddler + Appium + Mitmproxy + Android Emulator

IP Cores that can be used within Vivado

An old version of lwip and an old version of nxp driver. I am mystified why so many people star and fork this...

[SPGI 2018 Summer] - Project: A Tutorial to Web Applications Using Python Flask

FlowBlaze: Stateful Packet Processing in Hardware

To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture rec…

Multi-Generator (MGEN) traffic generation tool

A collection of popular design patterns implemented in TCL language with TclOO package