419 Open source projects that are alternatives of or similar to ofdm

Chisel 3: A Modern Hardware Design Language

Rocket Chip Generator

Quasar 2.0: Chisel equivalent of SweRV-EL2

Provides dot visualizations of chisel/firrtl circuits

A Hardware Construct Language

high-performance RTL simulator

Repository for basic (and not so basic) Verilog blocks with high re-use potential

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Docker Development Environment for SpinalHDL

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Test suite designed to check compliance with the SystemVerilog standard.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Virtio implementation in SystemVerilog

Various HDL (Verilog) IP Cores

FPGA-based RISC-V CPU+SoC.

SpinalHDL - Cryptography libraries

Haskell library for hardware description

OpenROAD's unified application implementing an RTL-to-GDS Flow

Code generation tool for configuration and status registers

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Recipe for FPGA cooking

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Sphinx Extension which generates various types of diagrams from Verilog code.

FPGA-based JPEG-LS image compressor.

Imitate SDcard using FPGAs.

Facilitates building open source tools for working with hardware description languages (HDLs)

Test suite designed to check compliance with the SystemVerilog standard.

Scala based HDL

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Ruby interface to IEEE 1364-2005 Verilog VPI

ZX Spectrum CPLD-based clone for rubber case

PostCSS plugin that polyfill Bi-directional CSS properties and values to suppot rtl and ltr rules in all browsers

A right-to-left theme for Jekyll with Jalali support and some other goodies.

Robotic Application Processor

Documentatin for YatCPU

Add right-to-left support to the NativeScript framework

Project Oberon (New Edition 2013) Unofficial Mirror

👌🏼 CoreUI is free bootstrap admin template. http://coreui.io

Verilog grammar for tree-sitter

RTL version of materializecss framework v1.0.0

Scripts to build and use docker images including GHDL

C++17 implementation of an AST for Verilog code generation

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

RTL layout for Laravel Nova.

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

List of ideas for getting started with TimVideos projects

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Simple way to set RTL for materializecss.com.

Efficient implementations of the transcendental functions

A full-speed device-side USB peripheral core written in Verilog.

PCIe (1.0a to 2.0) Virtual host model for verilog

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

OOUI is a modern JavaScript UI library with strong cross-browser support. It is the standard library for MediaWiki and Wikipedia. This is a mirror from https://gerrit.wikimedia.org. Main website: