703 Open source projects that are alternatives of or similar to Basic_verilog

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

Package manager and build abstraction tool for FPGA/ASIC development

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Verilog library for ASIC and FPGA designers

Library to stream in rtmp and rtsp for Android. All code in Java

The JAVE (Java Audio Video Encoder) library is Java wrapper on the ffmpeg project

Chisel 3: A Modern Hardware Design Language

Turning .NET assemblies into FPGA hardware for faster execution and lower power usage. See the Readme and https://hastlayer.com.

Open source ultrasound processing modules and building blocks

FPGA,Verilog,Python

a simple jpeg codec.

A litecoin scrypt miner implemented with FPGA on-chip memory.

Arduino generic menu/interactivity system

A refreshed Python toolbox for building complex digital hardware

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

Ham Radio hat for Raspberry PI

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Caffe to VHDL

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Reed Solomon BCH encoder and decoder

This is the main repository for all the examples for the book Practical UVM

Platform-Agnostic Security Tokens implementation in GO (Golang)

FPGA implementation of Cellular Neural Network (CNN)

🚂 Decodes url.Values into Go value(s) and Encodes Go value(s) into url.Values. Dual Array and Full map support.

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

A robust JavaScript implementation of a UTF-8 encoder/decoder, as defined by the Encoding Standard.

Official implementation of "Desinging an Encoder for StyleGAN Image Manipulation" https://arxiv.org/abs/2102.02766

A node utility utilizing ffmpeg to encode videos with the hevc codec.

fastest JSON encoder/decoder with powerful stream API for Golang

PicoRV32 - A Size-Optimized RISC-V CPU

Go module for encoding structs into URL query parameters

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

SD card based multi-purpose cartridge for the SNES

一步一步写MIPS CPU

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

Synchronize your subtitles using machine learning

XML Schema validator and data conversion library for Python

small C GIF encoder

The amqp tools such as delay strategies and so on.

SweRV EH1 core

Bitcoin miner for Xilinx FPGAs

Handy Swift features that didn't make it into the Swift standard library.

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

FFmpegCommand适用于Android的FFmpeg命令库，实现了对音视频相关的处理，能够快速的处理音视频，大概功能包括：音视频剪切，音视频转码，音视频解码原始数据，音视频编码，视频转图片或gif，视频添加水印，多画面拼接，音频混音，视频亮度和对比度，音频淡入和淡出效果等

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

A refreshed Python toolbox for building complex digital hardware

Non-blocking library for delaying function calls

Arduino FOC for BLDC and Stepper motors - Arduino Based Field Oriented Control Algorithm Library

A very primitive but hopefully self-educational CPU in Verilog

A tiny Open POWER ISA softcore written in VHDL 2008

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

A small 6502 system with MS BASIC in ROM

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

SPI master and slave for FPGA written in VHDL

A Verilog implementation of DisplayPort protocol for FPGAs

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

a simple and cheap vector network analyzer, including support software