712 Open source projects that are alternatives of or similar to dcurl

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

RISC-V Cores, SoC platforms and SoCs

VT220-compatible console on Cyclone IV EP4CE55F23I7

Machine learning in FPGAs using HLS

A simple brute forcer written in GO for SHA1, SHA256, SHA512, MD5 and bcrypt

Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

SystemOT, yet another home brew cpu.

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

A compiler, assembler, and processor.

GPU and vector-enabled map projections, geodesic calculations, and image warping 🌎🌍🌏

The OpenCL Utility library

Upduino v2 with the ice40 up5k FPGA demos

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

DaCe - Data Centric Parallel Programming

SweRV EH1 core

GPU Mersenne primality test.

Generator of verilog description for FPGA MobileNet implementation

Brevitas: quantization-aware training in PyTorch

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

中文版 Parallel Programming for FPGAs

Low-cost ECP5 FPGA development board

SHA-256 IP core for ZedBoard (Zynq SoC)

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

Portable 128-bit SIMD intrinsics

PCI Express DIY hacking toolkit for Xilinx SP605

Polyphony is Python based High-Level Synthesis compiler.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Accelerated Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian10 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc)

The OpenPiton Platform

IOTA Flash channels demo using webRTC for communication.

RISC-V CPU Core (RV32IM)

🎯 soap - Structural Optimisation of Arithmetic Programs

DMA source and sink blocks for Xilinx Zynq FPGAs

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

QKeras: a quantization deep learning library for Tensorflow Keras

Optimized string search routines for Rust.

CMod-S6 SoC

Example code you can run in Fastly Terrarium: https://www.fastlylabs.com/

usb-jtag - Altera USB Blaster Emulation with a FX2

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

An experiment for building gateware for the axiom micro / beta using nmigen and yosys

fast wasm modules

An example of how to use the Xilinx ISE toolchain from the command line

Easy function multiversioning for Rust

Library of approximate arithmetic circuits

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Common elements for FPGA Design (FIFOs, RAMs, etc.)

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Cython bindings and Python interface to Prodigal, an ORF finder for genomes and metagenomes. Now with SIMD!

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

An interactive OpenCL wavefront path tracer

Scots Army Knife for electronics

GPGPU microprocessor architecture

CLBLAS integration for Julia

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

SystemRDL 2.0 language compiler front-end

Managed Machine Learning Systems and Internet of Things Live Lesson