589 Open source projects that are alternatives of or similar to hdelk

System on Chip toolkit for Amaranth HDL

microcontroller-based FPGA / JTAG programmer

IceChips is a library of all common discrete logic devices in Verilog

View biological networks via Cytoscape.js and sbgn-ml

Node-based Blender game engine and logic editor addon for Blender

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Import and export IP-XACT XML register models

FPGA-based JPEG-LS image compressor.

328eForth for Arduino with mods for coinForth

Upduino v2 with the ice40 up5k FPGA demos

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

My 2,700 visio 🎨 shapes, stencils, symbols, and icons collection to visually represent IT infrastructure

A Repository of Benchmark Graph Datasets for Graph Classification (31 Graph Datasets In Total).

IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors

Project is in active development and has been moved to the EthereumJS VM monorepo.

Graph convolution with tf.keras

Virtual development board for HDL design

Matrix Functions for Teaching and Learning Linear Algebra and Multivariate Statistics, http://friendly.github.io/matlib/

R Interface for GraphFrames

OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing

New Algorithms for Learning on Hypergraphs

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Drop In USB CDC ACM core for iCE40 FPGA

GPIB IEEE 488.1 core

Chart.js Graph-like Charts (tree, force directed)

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)

FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit

Object-Role Modeling diagrams in TeX

Yet Another VHDL tool

Clash implementation of the Compucolor II home computer

Generic immutable recursive data representation API targeted at source code models and more.

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Draw ASCII diagrams in Neovim

A library for graph analysis written Julia.

An open-source VHDL library for FPGA design.

Graph IO functionality for various formats.

A comprehensive dimensional reduction framework to recover the latent topology from high-dimensional data.

a node-red application with balena-supervisor support, can be managed remotely via balena publicURL

A collection of little open source FPGA hobby projects

NN on FPGA

Schematic symbol libraries for FPGAs & microcontrollers.

A library of supporting code for numerical modelling (JSON config, HDF5 data, Modern OpenGL visualization)

Conditional Structure Generation through Graph Variational Generative Adversarial Nets, NeurIPS 2019.

A Library for visualizing Neural Networks of the TensorFlow/Keras models.

MOS6581 SID chip emulator in SystemVerilog

A python implementation of Patchy-San Convolutional Network for Graph

AXI support for Migen/MiSoC

No description or website provided.

Relational State Machine with a visual inspector

Unofficial Yosys WebAssembly packages

Hardware-accelerated Multi-threaded IOTA PoW, drop-in replacement for ccurl

Chisel components for FPGA projects

HDMI Out VHDL code for 7-series Xilinx FPGAs

VT220-compatible console on Cyclone IV EP4CE55F23I7

High-speed LaserDisc RF sampler

Julia hybrid constraint programming solver enhanced by a reinforcement learning driven search.

Revengineered ancient PDP-11 CPUs, originals and clones

Diagrams for visualizing neural network architecture (Created with diagrams.net)

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.