316 Open source projects that are alternatives of or similar to Heterocl

The Antikernel operating system project

HLS branch of Halide

An Open Source Deep Learning Inference Engine Based on FPGA

Compact FPGA game console

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

a simple and cheap vector network analyzer, including support software

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

LicheeTang 蜂鸟E203 Core

A mixed signal netlist language (pre-alpha)

FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian10 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc)

SystemRDL 2.0 language compiler front-end

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

SweRV EL2 Core

All open source file and project for OpenFPGAduino project

Example designs showing different ways to use SymbiFlow toolchains.

Connectal is a framework for software-driven hardware development.

High throughput JPEG decoder in Verilog for FPGA

Build Customized FPGA Implementations for Vivado

FPGA 101 - Workshop materials

A utility for Composing FPGA designs from Peripherals

SPI master and slave for FPGA written in VHDL

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

A MIPS CPU implemented in Verilog

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

A Video display simulator

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

FPGA-based RISC-V CPU+SoC.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Implementations of the Simon and Speck Block Ciphers

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

A reimplementation of a tiny stack CPU

i8080 precise replica in Verilog, based on reverse engineering of real die

FPGA Sega in Verilog, for Xilinx Virtex, circa 2002. Has an emulator thrown in, to simplify FPGA debugging.

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Caffe to VHDL

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Code generation tool for configuration and status registers

A simple, basic, formally verified UART controller

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

DaCe - Data Centric Parallel Programming

A wishbone controlled scope for FPGA's

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

A FPGA friendly 32 bit RISC-V CPU implementation

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Human Resource Machine - CPU Design #HRM

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Scots Army Knife for electronics

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3

PlutoSDR Firmware

Space Invaders game implemented with VHDL

A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

GPGPU microprocessor architecture