93 Open source projects that are alternatives of or similar to K210 Hal

MDEPX — A BSD-style RTOS

Sedna - a pure Java RISC-V emulator.

xv6-riscv like OS written in Rust

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

Jonesforth RISC-V port.

RISC-V processor emulator written in Rust+WASM

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

异步内核就像风一样快！

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

SoC based on VexRiscv and ICE40 UP5K

A self-hosting and educational C compiler

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

SweRV EH1 core

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Nuclei Microcontroller Software Interface Standard Development Repo

pulp_soc is the core building component of PULP based SoCs

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

Yet Another RISC-V Implementation

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.

⛔ DEPRECATED ⛔ HERO Software Development Kit

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

This repo contains the artifact for our SOSP'19 paper on Serval

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

RISCV SoftCPU Contest 2018

RARS -- RISC-V Assembler and Runtime Simulator

RISC-V SystemC-TLM simulator

Maxine VM: A meta-circular research VM

ARV: Asynchronous RISC-V Go High-level Functional Model

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The Gee (寂) Operating System, written in YuLang.

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

RISC-V RV32I[MAC] emulator with ELF support

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Simple risc-v emulator, able to run linux, written in C.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

A RISC-V simulator

Quasar 2.0: Chisel equivalent of SweRV-EL2

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Yet another toy CPU.

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

Nuclei RISC-V Software Development Kit

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

UNIX-like operating system written in C and C++

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

bl602 serial flasher

RISC-V Assembler and Runtime Simulator

A kernel written in Rust

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V simulator for x86-64

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Documentatin for YatCPU