561 Open source projects that are alternatives of or similar to Octavo

🌟 Alhambra II FPGA board

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

HW Design: A Functional Approach

Small-scale Tensor Processing Unit built on an FPGA

A JSON library implemented in VHDL.

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

ZX-Poly platform info page and its emulator. It is a multi-CPU ZXSpectrum clone.

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

Real-time binocular stereo vision FPGA system with OV5640 cameras

Accessible ♿️, Delightful ✨, & Fast 🚀

An Open Source configuration of the Arty platform

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Web-based HDL diagramming tool

Advanced Developer Async Programming Toolkit

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

i8080 precise replica in Verilog, based on reverse engineering of real die

GPIB IEEE 488.1 core

🎯 soap - Structural Optimisation of Arithmetic Programs

A collection of little open source FPGA hobby projects

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

328eForth for Arduino with mods for coinForth

Mesh-based Monte Carlo (MMC)

Transient Array Radio Telescope

DaCe - Data Centric Parallel Programming

An open-source VHDL library for FPGA design.

Library to write messages on top of game window

FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Mostly AVR compatible FPGA soft-core

⚡️ Fast async task based Swift framework with focus on type safety, concurrency and multi threading

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Scots Army Knife for electronics

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

PandA-bambu public repository

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

Accelerated Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

RingoJS is a JavaScript platform built on the JVM and optimized for server-side applications.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

A Video display simulator

IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors

Binary Neural Network on IceStick FPGA.

Chisel components for FPGA projects

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

H2O is an Open Source, Distributed, Fast & Scalable Machine Learning Platform: Deep Learning, Gradient Boosting (GBM) & XGBoost, Random Forest, Generalized Linear Modeling (GLM with Elastic Net), K-Means, PCA, Generalized Additive Models (GAM), RuleFit, Support Vector Machine (SVM), Stacked Ensembles, Automatic Machine Learning (AutoML), etc.

DMA source and sink blocks for Xilinx Zynq FPGAs

FPGA-based RISC-V CPU+SoC.

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

Overlay library for Angular 7+

HAL – The Hardware Analyzer

Implementations of the Simon and Speck Block Ciphers

Lipsi: Probably the Smallest Processor in the World

This overlay host is to provide a desktop overlay for when you're playing games in the browser and still want to see who's talking (such as TTRPGs on FoundryVTT or Roll20).

This project demonstrates DSP capabilities of Terasic DE2-115

P4-14/16 Bluespec Compiler

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Database connections for multi-threaded environments

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication