OpenpitonThe OpenPiton Platform
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Neo430A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
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e-verestEVEREST: e-Versatile Research Stick for peoples
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FPGACosmacELFA re-creation of a Cosmac ELF computer, Coded in SpinalHDL
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Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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Forth CpuA Forth CPU and System on a Chip, based on the J1, written in VHDL
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SHA256HasherSHA-256 IP core for ZedBoard (Zynq SoC)
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xup compute accelerationHands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
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processorA simple and lightweight JavaScript data processing tool. Live demo:
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tapascoThe Task Parallel System Composer (TaPaSCo)
Stars: ✭ 66 (+0%)
polyphonyPolyphony is Python based High-Level Synthesis compiler.
Stars: ✭ 90 (+36.36%)
yahdlA programming language for FPGAs.
Stars: ✭ 20 (-69.7%)
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (+392.42%)
react-layer-stackLayering system for React. Useful for popover/modals/tooltip/dnd application
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xedaCross EDA Abstraction and Automation
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toppyOverlay library for Angular 7+
Stars: ✭ 81 (+22.73%)
drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
Stars: ✭ 66 (+0%)
horizoverlayA simple horizontal damage meter overlay for Final Fantasy XIV. It currently shows player dps, damage %, hps, max hit, encounter duration and total dps. It's super configurable! It supports English, Portuguese, Chinese (S/T) and French.
Stars: ✭ 118 (+78.79%)
portshakerMaintain a set of FreeBSD ports trees.
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HexTagsCustomize tags & chat colors!
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tree-core-ideThe next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Stars: ✭ 79 (+19.7%)
foxpagesVisual FoxPro Multithread Web Server
Stars: ✭ 22 (-66.67%)
ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
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AdvisorA Hearthstone Deck Tracker plugin which tries to guess the opponent's deck while playing and shows it's supposed cards.
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tree-core-cpuA series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Stars: ✭ 22 (-66.67%)
fpga torture🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
Stars: ✭ 23 (-65.15%)
hBPFhBPF = eBPF in hardware
Stars: ✭ 335 (+407.58%)
tiny-tpuSmall-scale Tensor Processing Unit built on an FPGA
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soap🎯 soap - Structural Optimisation of Arithmetic Programs
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game overlay sdkLibrary to write messages on top of game window
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FPGAmp720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
Stars: ✭ 190 (+187.88%)
bnn-icestickBinary Neural Network on IceStick FPGA.
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captouch👇 Add capacitive touch buttons to any FPGA!
Stars: ✭ 96 (+45.45%)
zc pcie dmaDMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC
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super-workers🐴 Distribute load on front-end via parallelism
Stars: ✭ 93 (+40.91%)
vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (-27.27%)
CoyoteFramework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
Stars: ✭ 80 (+21.21%)
kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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shdl6800shdl6800: A 6800 processor written in SpinalHDL
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fpbinaryFixed point package for Python.
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pineconePeer-to-peer overlay routing for the Matrix ecosystem
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FPGA UltrasoundCMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
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yafpgatetrisYet Another Tetris on FPGA Implementation
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Awesome-Retro-DocsA curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
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basic-ecp5-pcbReference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
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processorA compiler, assembler, and processor.
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awesome-hwd-toolsA curated list of awesome open source hardware design tools
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SpinalDevDocker Development Environment for SpinalHDL
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os-xtooThe Java and Enlightenment ebuild repository
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