304 Open source projects that are alternatives of or similar to Potato

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting

Various projects for the Nexys4DDR board from Digilent

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Second version of homemade 30 MHz - 6 GHz VNA

Caffe to VHDL

RISC-V instruction set simulator built for education

Component video modification for the C64 8-bit computer

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.

ECE368 | Lab

AutoPkg recipes all the way from Seattle, WA.

A FPGA friendly 32 bit RISC-V CPU implementation

Open source software for chip reverse engineering.

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

CoreFreq is a CPU monitoring software designed for the 64-bits Processors.

LicheeTang 蜂鸟E203 Core

Donjon hardware tool for circuits security evaluation

v3.5 https://rcore-os.github.io/rCore-Tutorial-Book-v3/

Example code for the Numato Opsis board, the first HDMI2USB production board.

🖥️ An xv6-like operating system on RISC-V with multi-core support. Documentation available online.

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

A VHDL frontend for Yosys

SST Architectural Simulation Components and Libraries

C++17 RISC-V RV32GC / RV64GC userspace emulator library

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

BL602 SDK. Any technical topic, please access the following link.

Image Processing Toolbox in Verilog using Basys3 FPGA

RISC-V CPU Core

Alphanumeric+1 shellcoding tools for RISC-V

Compact FPGA game console

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Acorn BBC Micro on an Altera DE1 FPGA board

A pipelined RISCV implementation in VHDL

Space Invaders game implemented with VHDL

Simple custom computer on a FPGA

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

AES-128 hardware implementation

The Zylin ZPU

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

Xilinx Deep Learning IP

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

Jest HTML Reporter and Results Processor

A Audio Interface for the Zedboard

Processor Counter Monitor

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

An implementation of original SHA-256 hash function in (RTL) VHDL

RISC-V Instruction Set Simulator (Built for education).

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

A work-in-progress for what is to be a software-free web server for static content.

OpenEmbedded/Yocto layer for RISC-V Architecture

Intel(R) Xeon(R) Processor Max Effort Turbo Boost UEFI DXE driver

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Scala based HDL

FPGA-based HDMI ambient lighting

A Bitcoin miner for the Zynq chip utilizing the Zedboard.

Implementations of the Simon and Speck Block Ciphers