342 Open source projects that are alternatives of or similar to Project Zipline

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

iCESugar FPGA Board (base on iCE40UP5k)

Open source design files for the TinyFPGA B-Series boards.

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

🌱 ❄️ Collection of open-source peripherals in Verilog

The USRP™ Hardware Driver FPGA Repository

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

A Verilog HDL model of the MOS 6502 CPU

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

SystemVerilog parser library fully complient with IEEE 1800-2017

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA/hardware design of openwifi

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

32-bit Superscalar RISC-V CPU

Repository for the SCALE-MAMBA MPC system

Verilog UART

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

synthesiseable ieee 754 floating point library in verilog

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Verilog I2C interface for FPGA implementation

A simple, basic, formally verified UART controller

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

All code found on nandland is here. underconstruction.gif

CHIP-8 console on FPGA

Recipe for FPGA cooking

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

BaseJump STL: A Standard Template Library for SystemVerilog

Hardware implementation of the SHA-256 cryptographic hash function

Small footprint and configurable PCIe core

Open source software for chip reverse engineering.

Bus bridges and other odds and ends

SystemVerilog to Verilog conversion

Open source implementation of a x86 processor

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

SystemVerilog compiler and language services

Notes on the Red Pitaya Open Source Instrument

Chisel 3: A Modern Hardware Design Language

一步一步写MIPS CPU

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

CNN acceleration on virtex-7 FPGA with verilog HDL

All open source file and project for OpenFPGAduino project

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

FPGA-based Nintendo Entertainment System Emulator

LicheeTang 蜂鸟E203 Core

A Compiler for the Popr Language

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

A High-performance Timing Analysis Tool for VLSI Systems

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Verilog SDRAM memory controller

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

A litecoin scrypt miner implemented with FPGA on-chip memory.

An open source SPI flash emulator and monitor

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Verilog Generator of Neural Net Digit Detector for FPGA

FPGA,Verilog,Python