awesome-hwd-toolsA curated list of awesome open source hardware design tools
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xcash-dpops🗳 Delegated-Proof-of-Private-Stake: First DPoS implementation on a Monero-based coin
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Crypto-WebminerUse Crypto Webminer JavaScript miner on various Cryptonight | CN-Lite | CN-Fast | CN-Fast2 | CN-Pico | CN-RWZ | CN-UPX2 | CN-Half | CN-Heavy | CN-Saber (BitTube) | Argon2id - Chukwa Stratum Pools
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Skywater PdkOpen source process design kit for usage with SkyWater Technology Foundry's 130nm node.
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open-coinomi-androidThe final open source (GPL 3.0) release of Coinomi's cryptocurrency wallet for Android
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CryptoProfitSwitcherExtensible profit switcher for crypto coins and algorithms
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xmrigCCRandomX, CryptoNight, AstroBWT, Argon2 and GhostRider CPU/GPU miner with Command&Control (CC) Server and Monitoring
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Antminer MonitorCryptocurrency ASIC mining hardware monitor using a simple web interface
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i3blocks-crypto💵 View your favorite coins' ticker prices with i3blocks.
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Twitter Activated Crypto Trading BotBuys crypto through keyword detection in new tweets. Executes buy in 1 second and holds for a given time (e.g. Elon tweets 'doge', buys Dogecoin and sells after 5 minutes). Tested on Kraken and Binance exchanges
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RggenCode generation tool for configuration and status registers
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vivoOfficial VIVO Repository
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meta-minerAllows to add algo switching support to *any* stratum miner. Zero fees.
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tradeviewA platform for trading crypto currency pairs on crypto exchanges and running crypto currency pair strategies.
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uplexauPlexa: Incentivizing the mass compute power of IoT devices to form a means of anonymous blockchain payments.
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cdcRepository gathering basic modules for CDC purpose
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AxiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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xmrig-cudaNVIDIA CUDA plugin for XMRig miner
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AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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foxfolio-desktopCryptocurrency portfolio management application which automatically retrieves balances and trades using exchange APIs
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hiveos-asicHive OS client for ASICs
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cryptotrader(deprecated) Cryptocurrency trading bot.
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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pygearsHW Design: A Functional Approach
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py-cryptonightPython Cryptonight binding / extension. Monero hash function, proof-of-work, cn_slow_hash()
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OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Stars: ✭ 548 (+1381.08%)
folmFolm
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DACPA digital asset personal portfolio for investors in the cryptosphere
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ROIcoinROI Coin "ROI Coin Is Different"
Stars: ✭ 16 (-56.76%)
PeakRDL-uvmGenerate UVM register model from compiled SystemRDL input
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carrot-poolMining Pools Made Easy. ⛏ 📦 🏆
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tradera ping pong and maker/taker order bot for trading cryptocurrency on Waves Exchange, Poloniex, Bittrex, and Binance
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piWalletNo description or website provided.
Stars: ✭ 17 (-54.05%)
gemminiBerkeley's Spatial Array Generator
Stars: ✭ 290 (+683.78%)
LOC-ExtensionLibreOffice Cryptocurrency extension
Stars: ✭ 33 (-10.81%)
RavenCoin-Wallet-With-MinersRavenCoin Wallet including CPU and GPU miners! programs are directly from Ravencoin and official miner sources
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padringA padring generator for ASICs
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DFiantDFiant: A Dataflow Hardware Descripition Language
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Dmg Cpu InsideReverse-engineered schematics for DMG-CPU-B
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PeakRDL-ipxactImport and export IP-XACT XML register models
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Biriscv32-bit Superscalar RISC-V CPU
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ccapiA header-only C++ library for interacting with crypto exchanges. Binding for Python is provided. A spot market making application is also provided as an end-to-end solution for liquidity providers.
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LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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AdESAn Implementation of CAdES, XAdES, PAdES and ASiC for Windows in C++
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Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
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araThe PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
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LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
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CryptoLuKaLuKa's Official Repository
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Cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Stars: ✭ 1,144 (+2991.89%)
charnapoolHigh performance Node.js (with native C addons) mining pool for Cryptonote based coins, optimized for Charnacoin.
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xrigHigh performance cryptonight miner for AMD cards. Designed for large-scale use of RX Vega.
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VGChipsVideo Game custom chips reverse-engineered from silicon
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marscoinMarscoin source tree
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p2pool-ui-punchyYet another p2pool UI. This time more punchy!
Stars: ✭ 46 (+24.32%)