93 Open source projects that are alternatives of or similar to Riscy

RISCV SoftCPU Contest 2018

RISC-V RV32I[MAC] emulator with ELF support

Maxine VM: A meta-circular research VM

A kernel written in Rust

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

RISC-V Assembler and Runtime Simulator

ARV: Asynchronous RISC-V Go High-level Functional Model

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

Nuclei RISC-V Software Development Kit

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RISC-V SystemC-TLM simulator

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

The Gee (寂) Operating System, written in YuLang.

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

Simple risc-v emulator, able to run linux, written in C.

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

A RISC-V simulator

RARS -- RISC-V Assembler and Runtime Simulator

Yet another toy CPU.

Quasar 2.0: Chisel equivalent of SweRV-EL2

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

Jonesforth RISC-V port.

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

⛔ DEPRECATED ⛔ HERO Software Development Kit

RISC-V simulator for x86-64

Documentatin for YatCPU

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

A FPGA friendly 32 bit RISC-V CPU implementation

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

MDEPX — A BSD-style RTOS

A self-hosting and educational C compiler

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Tests for example Rocket Custom Coprocessors

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

RISC-V processor emulator written in Rust+WASM

pulp_soc is the core building component of PULP based SoCs

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Sedna - a pure Java RISC-V emulator.

Nuclei Microcontroller Software Interface Standard Development Repo

Yet Another RISC-V Implementation

SonicBOOM: The Berkeley Out-of-Order Machine

异步内核就像风一样快！

xv6-riscv like OS written in Rust

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

SweRV EH1 core

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

FPGA 101 - Workshop materials

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).