184 Open source projects that are alternatives of or similar to Rocket Chip

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Chisel Things for OFDM

Quasar 2.0: Chisel equivalent of SweRV-EL2

Chisel 3: A Modern Hardware Design Language

high-performance RTL simulator

SweRV EH1 core

Simple RISC-V 3-stage Pipeline in Chisel

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

FPGA-based RISC-V CPU+SoC.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SweRV EL2 Core

SoC based on VexRiscv and ICE40 UP5K

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

Scala based HDL

🌍 Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

Enabling bidirectional support on tailwindcss framework

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

RISC-V simulator for x86-64

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

homebrew (macOS) packages for RISC-V toolchain

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

PostCSS plugin that lets you control your layout (LTR or RTL) through logical rather than physical rules

bootstrap 3 arabic

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

riscv资料、论文等

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab…

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

OpenEmbedded/Yocto layer for RISC-V Architecture

Riscy Processors - Open-Sourced RISC-V Processors

RARS -- RISC-V Assembler and Runtime Simulator

RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic

Do you want RTL ActionBar? So you've found a library that can RTLize android's "ActionBar"!

An unofficial reference sheet for RISC-V.

FPGA 101 - Workshop materials

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Test suite designed to check compliance with the SystemVerilog standard.

Code generation tool for configuration and status registers

A library which configures a divider for a RecyclerView.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Tests for example Rocket Custom Coprocessors

RISC-V Assembler and Runtime Simulator

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

this is an RTL Version of sb-admin2 Template, one of free template series in startbootstrap.com , (download remain file from startbootstrap.com)

ViewPager with RTL support 🔄

A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

A FPGA friendly 32 bit RISC-V CPU implementation

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.