579 Open source projects that are alternatives of or similar to verismith

PDP-6 Emulator

A support library for Ronin. Like activesupport, but for hacking!

SOLTIX: Scalable automated framework for testing Solidity compilers.

run AFL with pintool

X41 Smartcard Fuzzer

Sample files for fuzzing ImageMagick

This is a repo is to upload files done during my research.

HDLBits website practices & solutions

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

AFL "mostly" ported to cygwin

NN on FPGA

run AFL with dynamorio

Standard Cell Library based Memory Compiler using FF/Latch cells

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

FPGA-based JPEG-LS image compressor.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

A fast SAT solver

A grammar-based custom mutator for AFL++

Generator of verilog description for FPGA MobileNet implementation

Automatic function exporting and linking for fuzzing cross-architecture binaries.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Mutation Based Fuzzer for IEC61850 Server IED'S

Fuzzer to automatically find side-channel (timing) vulnerabilities

OpenType font file format fuzzer for Windows

A Python3 module to assist in fuzzing web applications

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Fuzzware's main repository. Start here to install.

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Trying to verify Verilog/VHDL designs with formal methods and tools

yet another dirbuster

StateAFL: A Greybox Fuzzer for Stateful Network Servers

libdft for Intel Pin 3.x and 64 bit platform. (Dynamic taint tracking, taint analysis)

Challenging testcases for fuzzers

Virtual development board for HDL design

Fuzz testing for jest

Foundry is a blazing fast, portable and modular toolkit for Ethereum application development written in Rust.

AFL binary instrumentation

SpinalHDL - Cryptography libraries

"Seed Selection for Successful Fuzzing" artifact (at ISSTA 2021)

expansion of afl-unicorn using c++

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

A collection of user-space Linux kernel specific guided fuzzers based on LKL

Improving security and resilience of WebAssembly VMs/runtimes/parsers using fuzzing

FirmWire is a full-system baseband firmware emulation platform for fuzzing, debugging, and root-cause analysis of smartphone baseband firmwares

Swift-based fuzzing tools

🎯 A collection of fuzzing targets written in Rust.

Find exploitable PHP files by parameter fuzzing and function call tracing

Simple 3-stage pipeline RISC-V processor

Yet Another RISC-V Implementation

MOS6581 SID chip emulator in SystemVerilog

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

A simple program reducer for any language.

Revengineered ancient PDP-11 CPUs, originals and clones

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Reads a state transition system and performs property checking

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm