248 Open source projects that are alternatives of or similar to yavhdl

Cross EDA Abstraction and Automation

Virtual development board for HDL design

HDL symbol generator

ACT hardware description language and core tools.

An abstraction library for interfacing EDA tools

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

VHDL formatter web online written in typescript

This is a project based on the FIFA World Cup 2019 and Analyzes the Performance and Efficiency of Teams, Players, Countries and other related things using Data Analysis and Data Visualizations

shdl6800: A 6800 processor written in SpinalHDL

Plugin to generate BOM + CPL files for JLCPCB, assigning LCSC part numbers directly from the plugin, query the JLCPCB parts database, lookup datasheets and much more.

Chinese NLP Data Augmentation， BERT Contextual Augmentation

Discover, Explore and Document your Event Driven Architectures powered by Markdown.

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

HDMI Out VHDL code for 7-series Xilinx FPGAs

WAL enables programmable waveform analysis.

A padring generator for ASICs

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

Sphinx Extension which generates various types of diagrams from Verilog code.

Docker Development Environment for SpinalHDL

RISC-V by VectorBlox

Virtio implementation in SystemVerilog

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

[WIP] Dockerize Synopsys/Cadence EDA tools

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Generate descriptive statistics

Powerful rapid automatic EDA and feature engineering library with a very easy to use API 🌟

Facilitates building open source tools for working with hardware description languages (HDLs)

An implementation of DisplayPort protocol for FPGAs

👇 Add capacitive touch buttons to any FPGA!

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

A C# library wrapping some of KiCad's functionallity, allowing for some features not in the software and programmatic circuit creation

Library for working with KiCAD file formats

@elahe-dastan / @1995parham training and testing repository 📚 🤓

AXI support for Migen/MiSoC

Interface for MSX to Connect and use Raspberry Pi resources

A simple I2C minion in VHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

This repository contains iCEBreaker examples for Amaranth HDL.

Are you ready to FLIRT with your wearable data?

Simple and Ideal Circuit Simulation

Tools for running FPGA vendor toolchains with Docker

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

A Forth CPU and System on a Chip, based on the J1, written in VHDL

A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo.

Functions for easily making publication-quality figures with matplotlib.

VHDL synthesis (based on ghdl)

OpenN@S: Open-source software to NAS automatic VHDL code generation

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A simple RISC-V processor for use in FPGA designs.

Open source software for chip reverse engineering.

Simple implementation of cache using VHDL

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Julia module for digital communication tools.