580 Open source projects that are alternatives of or similar to yosys

Sphinx Extension which generates various types of diagrams from Verilog code.

Mostly AVR compatible FPGA soft-core

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

A programming language for FPGAs.

P4-14/16 Bluespec Compiler

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

SneakySnake🐍 is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs…

👨‍🏫 BigBlueButton Python API

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

The universal Sentry release CLI 🚀

🎡 Build Python wheels for all the platforms on CI with minimal configuration.

FPGA Assembly (FASM) Parser and Generator

A GitHub Action that installs Python package dependencies from a user-defined requirements.txt file path with optional pip, setuptools, and wheel installs/updates

PyPI Simple Repository API client library

placekey.io

import caipyra module code

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

Command-line interface to Habitica

Yet Another Tetris on FPGA Implementation

Queues the sending of email with Django Q.

Virtio implementation in SystemVerilog

Fused multiply-add (with a single rounding) for Python.

Collection of easy to use, beginner friendly but powerful, orthogonal tools to speed up discord bots development (discord.py)

PyPi Mirror Manager

SHA-256 IP core for ZedBoard (Zynq SoC)

shdl6800: A 6800 processor written in SpinalHDL

No-MMU Linux capable RISC-V SoC designed to be useful.

Access domain information via python and command line.

A Vivado HLS Command Line Helper Tool

Programmable multichannel ADPCM decoder for FPGA

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

hBPF = eBPF in hardware

This repository contains iCEBreaker examples for Amaranth HDL.

Cira algorithmic trading made easy. A Façade library for simpler interaction with alpaca-trade-API from Alpaca Markets.

A powerful, colorful, beautiful command-line-interface for pypi.org

Cross EDA Abstraction and Automation

Copy iOS image resources to their appropriate Android directory

👇 Add capacitive touch buttons to any FPGA!

Lattice iCE40: development platform for PlatformIO

A Simple , ☁️ Lightweight , 💪 Efficent JSON based database for 🐍 Python. PysonDB-V2 has been released ⬇️

🖥️ Pretty tables in the terminal

Kansas Lava implementation of MOS 6502 microprocessor

iCE40 floorplan viewer

ndjson with the same interface as the builtin json module

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Hera is an Argo Workflows Python SDK. Hera aims to make workflow construction and submission easy and accessible to everyone! Hera abstracts away workflow setup details while still maintaining a consistent vocabulary with Argo Workflows.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

This project demonstrates DSP capabilities of Terasic DE2-115

Polyphony is Python based High-Level Synthesis compiler.

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

RISC-V Cores, SoC platforms and SoCs

Small-scale Tensor Processing Unit built on an FPGA

The Task Parallel System Composer (TaPaSCo)

HDMI Out VHDL code for 7-series Xilinx FPGAs

High-speed LaserDisc RF sampler

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)