342 Open source projects that are alternatives of or similar to Computerarchitecturelab

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

FPGA/AES/LeNet/VGG16

Mega CD for MiSTer

This is a higan/Verilator co-simulation example/framework

FPGA-based glitcher for the Digilent Arty FPGA development board.

RTL, Cmodel, and testbench for NVDLA

❄️ Visual editor for open FPGA boards

FPGA 101 - Workshop materials

Barerbones OSX based Verilog simulation toolchain.

This is the base project for the Mojo. It should be used as the starting point for all projects.

CoreIR Symbolic Analyzer

collaboration on work in progress

A FPGA friendly 32 bit RISC-V CPU implementation

Verilog and MIPS simple programs

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Image Processing Toolbox in Verilog using Basys3 FPGA

Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

A reimplementation of a tiny stack CPU

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

CNN accelerator

A mixed signal netlist language (pre-alpha)

Contains examples to start with Kactus2.

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

冯爱民老师《计算机组成原理A》课程设计

Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.

A wishbone controlled scope for FPGA's

Realtime VGA to ASCII Art converter

CDBUS Protocol and the IP Core for FPGA users

實作《自己動手寫CPU》書上的程式碼

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Haskell to VHDL/Verilog/SystemVerilog compiler

This is the main repository for all the examples for the book Practical UVM

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

Human Resource Machine - CPU Design #HRM

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

8MB FastRAM Board for the Amiga 500 & Amiga 500+

FuseSoC standard core library

The 99 Traveling Salespeople Project

Code generation tool for configuration and status registers

CAN Protocol Controller

My solutions to Alteras example labs

Change the pitch of your voice in real-time!

High throughput JPEG decoder in Verilog for FPGA

Galaksija computer for FPGA

Stuff from CTF contests

G.729 Encoder

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Featherweight RISC-V implementation

Example designs showing different ways to use SymbiFlow toolchains.

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

A small 6502 system with MS BASIC in ROM

A MIPS CPU implemented in Verilog