342 Open source projects that are alternatives of or similar to Fpu

Chisel 3: A Modern Hardware Design Language

LicheeTang 蜂鸟E203 Core

Verilog SDRAM memory controller

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

All open source file and project for OpenFPGAduino project

BaseJump STL: A Standard Template Library for SystemVerilog

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Recipe for FPGA cooking

SystemVerilog to Verilog conversion

SystemVerilog language server

一步一步写MIPS CPU

SystemVerilog compiler and language services

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

A Compiler for the Popr Language

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Notes on the Red Pitaya Open Source Instrument

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Bus bridges and other odds and ends

NES in Verilog

Hardware implementation of the SHA-256 cryptographic hash function

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

Verilog UART

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Repository for the SCALE-MAMBA MPC system

Open source design files for the TinyFPGA B-Series boards.

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

32-bit Superscalar RISC-V CPU

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Verilog I2C interface for FPGA implementation

iCESugar FPGA Board (base on iCE40UP5k)

Verilog Generator of Neural Net Digit Detector for FPGA

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

SystemVerilog parser library fully complient with IEEE 1800-2017

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

A simple, basic, formally verified UART controller

CHIP-8 console on FPGA

🌱 ❄️ Collection of open-source peripherals in Verilog

FPGA/hardware design of openwifi

All code found on nandland is here. underconstruction.gif

FPGA,Verilog,Python

PicoRV32 - A Size-Optimized RISC-V CPU

A Verilog HDL model of the MOS 6502 CPU

A Verilog implementation of DisplayPort protocol for FPGAs

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

The USRP™ Hardware Driver FPGA Repository

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

A High-performance Timing Analysis Tool for VLSI Systems

Small footprint and configurable PCIe core

FPGA-based Nintendo Entertainment System Emulator

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Open source software for chip reverse engineering.