442 Open source projects that are alternatives of or similar to Fwrisc

FPGA-based RISC-V CPU+SoC.

LicheeTang 蜂鸟E203 Core

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Yet Another RISC-V Implementation

List of ideas for getting started with TimVideos projects

Compact FPGA game console

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Homebrew game for homebrew FPGA game console

Simple 3-stage pipeline RISC-V processor

Small Processing Unit 32: A compact RV32I CPU written in Verilog

32-bit Superscalar RISC-V CPU

RISC-V CPU Core (RV32IM)

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Verilog implementation of the SHA-512 hash function.

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

SDRAM controller with multiple wishbone slave ports

High Speed Analog Front End FPGA Firmware for Novena PVT1

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

8MB FastRAM Board for the Amiga 500 & Amiga 500+

Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!

A demonstration showing how several components can be compsed to build a simulated spectrogram

tf530

Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

Fixed FCT proof for latest coq and ssreflect

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)

FPGA/AES/LeNet/VGG16

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Realtime VGA to ASCII Art converter

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.

Reko is a binary decompiler.

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

A Lenet ASIC Accelerator targeting minimum number of cycles

The 99 Traveling Salespeople Project

Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module

A very simple VGA controller written in verilog

冯爱民老师《计算机组成原理A》课程设计

This is a higan/Verilator co-simulation example/framework

Image Processing Toolbox in Verilog using Basys3 FPGA

Barerbones OSX based Verilog simulation toolchain.

mystorm sram test

1801 series ULA reverse engineering

CAN Protocol Controller

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

KT-Link compatible buffer for the Bus Blaster v3

Haskell to VHDL/Verilog/SystemVerilog compiler

CNN accelerator

A (very) minimal web browser for FPGAs implemented in Verilog

A CPU that implementing THCO-MIPS16 instruction set.

Change the pitch of your voice in real-time!

related to Spartan6 FPGA

This repo is for the 4618 group nember to share code.

實作《自己動手寫CPU》書上的程式碼