588 Open source projects that are alternatives of or similar to Nontrivial Mips

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

A MIPS CPU implemented in Verilog

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

A small, light weight, RISC CPU soft core

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A reimplementation of a tiny stack CPU

A FPGA friendly 32 bit RISC-V CPU implementation

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

32-bit Superscalar RISC-V CPU

RISC-V CPU Core (RV32IM)

Simple, orthogonal 32-bit computer architecture and environment

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Human Resource Machine - CPU Design #HRM

FPGA-based RISC-V CPU+SoC.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Managed Machine Learning Systems and Internet of Things Live Lesson

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A Forth CPU and System on a Chip, based on the J1, written in VHDL

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Android performance test

A set of Linux binary exploitation tasks for beginners on various architectures

Dataflow compiler for QNN inference on FPGAs

C--compiler which implements LL(1)\LR(0)\SLR\LR(1) and semantic analysis and MIPS generate

ILGPU JIT Compiler for high-performance .Net GPU programs

Brevitas: quantization-aware training in PyTorch

A lightweight high performance tensor algebra framework for modern C++

The OpenPiton Platform

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

SweRV EH1 core

macOS system monitor in your menu bar

中文版 Parallel Programming for FPGAs

Plasma is an interactive disassembler for x86/ARM/MIPS. It can generates indented pseudo-code with colored syntax.

Various HDL (Verilog) IP Cores

An abstraction library for interfacing EDA tools

iOS 任务调度器，为 CPU 和内存减负（用于性能优化）

Real-Time 3D Semantic Reconstruction from 2D data

极客时间专栏《许式伟的架构课》相关的源代码：冯诺伊曼结构

Universal utility for programming FPGA

Web Extension — A new tab page extension with material design and useful features 🆕 🎉

💻 A very simple redis monitor based on Flask and React. 一个部署简单的 redis 监控程序，使用 Flask 和 React 完成。

Bistoury是去哪儿网的java应用生产问题诊断工具，提供了一站式的问题诊断方案

QKeras: a quantization deep learning library for Tensorflow Keras

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

A Y86 pipeline CPU simulator in JavaScript.

Cross-platform process cpu % and memory usage of a PID

An open source library for image processing on FPGA.

RISC-V processor emulator written in Rust+WASM

CPU Based Rasterizer Engine

SDAccel Examples