1699 Open source projects that are alternatives of or similar to Nyuziprocessor

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Yet Another RISC-V Implementation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Generator of verilog description for FPGA MobileNet implementation

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

A full-speed device-side USB peripheral core written in Verilog.

Transient Array Radio Telescope

Wishbone controlled I2C controllers

A configurable C++ generator of pipelined Verilog FFT cores

List of ideas for getting started with TimVideos projects

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

qihoo360 xlearning with GPU support; AI on Hadoop

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Video Game custom chips reverse-engineered from silicon

Global Dark Mode for ALL apps on ANY platforms.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Haskell library for hardware description

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Various HDL (Verilog) IP Cores

An abstraction library for interfacing EDA tools

The OpenPiton Platform

Vulkan compute for people

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

GPGPU Javascript library 🐸

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

🌱 Open source ecosystem for open FPGA boards

Human Resource Machine - CPU Design #HRM

A mixed signal netlist language (pre-alpha)

FPGA 101 - Workshop materials

Particle-in-Cell Simulations for the Exascale Era ✨

Thin C++-flavored wrappers for the CUDA Runtime API

Verilog to Routing -- Open Source CAD Flow for FPGA Research

The Antikernel operating system project

Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group

💿 CD Content ( Source Code ) Collection of Book <GPU Gems > 1~ 3 | 《GPU精粹》 1~ 3 随书CD（源代码）珍藏

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

The USRP™ Hardware Driver Repository

High level plotting on the GPU.

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Automatic GPU, TPU, FPGA, Xeon Phi, Multithreaded, Distributed, etc. offloading for scientific machine learning (SciML) and differential equations

High-performance Bayesian Data Analysis on the GPU in Clojure

Image Processing Toolbox in Verilog using Basys3 FPGA

Haskell to VHDL/Verilog/SystemVerilog compiler

A MIPS CPU implemented in Verilog

❄️ Visual editor for open FPGA boards

A wishbone controlled scope for FPGA's

A FPGA friendly 32 bit RISC-V CPU implementation

Code generation tool for configuration and status registers

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

CUDA integration for Python, plus shiny features

Caffe to VHDL

High throughput JPEG decoder in Verilog for FPGA

A reimplementation of a tiny stack CPU

High-speed LaserDisc RF sampler

MOS6581 SID chip emulator in SystemVerilog

Android GPU Inspector